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In-Reply-To: <20240104-sm8150-dfs-support-v1-1-a5eebfdc1b12@quicinc.com>
References: <20240104-sm8150-dfs-support-v1-0-a5eebfdc1b12@quicinc.com> <20240104-sm8150-dfs-support-v1-1-a5eebfdc1b12@quicinc.com>
Subject: Re: [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
From: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey <quic_ajipan@quicinc.com>, Imran Shaik <quic_imrashai@quicinc.com>, Jagadeesh Kona <quic_jkona@quicinc.com>, Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Deepak Katragadda <dkatraga@codeaurora.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Rob Herring <robh+dt@kernel.org>, Satya Priya Kakitapalli <quic_skakitap@quicinc.com>, Taniya Das <quic_tdas@quicinc.com>, Vinod Koul <vkoul@kernel.org>
Date: Thu, 04 Jan 2024 13:36:41 -0800
User-Agent: alot/0.10

Quoting Satya Priya Kakitapalli (2024-01-04 06:23:04)
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 05d115c52dfe..6d76fd344ddf 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s=
0_clk_src[] =3D {
>         { }
>  };
> =20
> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D {

Can these be const?

> +       .name =3D "gcc_qupv3_wrap0_s0_clk_src",
> +       .parent_data =3D gcc_parents_0,
> +       .num_parents =3D ARRAY_SIZE(gcc_parents_0),
> +       .flags =3D CLK_SET_RATE_PARENT,
> +       .ops =3D &clk_rcg2_ops,
> +};
> +
>  static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D {
>         .cmd_rcgr =3D 0x17148,
>         .mnd_width =3D 16,
>         .hid_width =3D 5,
>         .parent_map =3D gcc_parent_map_0,
>         .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src,
> -       .clkr.hw.init =3D &(struct clk_init_data){
> -               .name =3D "gcc_qupv3_wrap0_s0_clk_src",
[...]
> @@ -3786,6 +3850,13 @@ static int gcc_sm8150_probe(struct platform_device=
 *pdev)
>         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
>         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
> =20
> +       ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> +                                      ARRAY_SIZE(gcc_dfs_clocks));
> +       if (ret) {
> +               dev_err(&pdev->dev, "Failed to register with DFS!\n");

Use=20

		return dev_err_probe(...);