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[147.75.80.249]) by mx.google.com with ESMTPS id v1-20020a056402348100b005573c695f4csi9735edc.513.2024.01.04.23.11.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 23:11:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-17537-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DXKBG+Ck; spf=pass (google.com: domain of linux-kernel+bounces-17537-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-17537-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 880AE1F22812 for ; Fri, 5 Jan 2024 07:11:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC79121A12; Fri, 5 Jan 2024 07:10:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DXKBG+Ck" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB25421A0A; Fri, 5 Jan 2024 07:10:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704438601; x=1735974601; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yI3vAwPncbVLavG81fYMbPZSPJAY88eIPqNf+iXAeL4=; b=DXKBG+Ck+Lgsb9JMy+ZrrnFHd3ti6O/OQLLL55Z3Sz9eGgG13bX9ITPa e+MKFcMoKibcfvD/5Oe6N4lt+2lAud/9KR+LudoWI/tpJhWq+q8Qf3e3u HYvYxrtLBn0wNEJcgg7P0Dy09AA3vHB0D58g7RB3WK9HnLPRAGsh3Klh5 wGoNTEYHMzGv32IZJcz6Tj8N3r2Jpk+el5UJ7PldfsSH4uaf51FU9eMWs OojYRAy9/TAVDqLGVxGyP/OKc81lGKvarGZqIMMwdQsWxr3Km+lpE1SBx QnAknxzI/YOFpvYfuLS/Rg6majpQNBZFTje+4+7FlrwCLuVvBW/4CURSV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="463845858" X-IronPort-AV: E=Sophos;i="6.04,333,1695711600"; d="scan'208";a="463845858" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 23:10:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="871167308" X-IronPort-AV: E=Sophos;i="6.04,333,1695711600"; d="scan'208";a="871167308" Received: from pg-esw-build.png.intel.com ([10.226.214.65]) by FMSMGA003.fm.intel.com with ESMTP; 04 Jan 2024 23:09:57 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Teoh Ji Sheng Subject: [PATCH net-next v2 3/4] net: stmmac: Add support for TX/RX channel interrupt Date: Fri, 5 Jan 2024 15:09:24 +0800 Message-Id: <20240105070925.2948871-4-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240105070925.2948871-1-leong.ching.swee@intel.com> References: <20240105070925.2948871-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Swee Leong Ching Enable TX/RX channel interrupt registration for MAC that interrupts CPU through shared peripheral interrupt (SPI). Per channel interrupts and interrupt-names are registered through, Eg: 4 tx and 4 rx channels: interrupts = , , , ; ; ; ; ; interrupt-names = "dma_tx0", "dma_tx1", "dma_tx2", "dma_tx3", "dma_rx0", "dma_rx1", "dma_rx2", "dma_rx3"; Signed-off-by: Teoh Ji Sheng Signed-off-by: Swee Leong Ching --- .../ethernet/stmicro/stmmac/stmmac_platform.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 70eadc83ca68..ae6859153e98 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -710,6 +710,10 @@ EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char irq_name[9]; + int i; + int irq; + memset(stmmac_res, 0, sizeof(*stmmac_res)); /* Get IRQ information early to have an ability to ask for deferred @@ -743,6 +747,30 @@ int stmmac_get_platform_resources(struct platform_device *pdev, dev_info(&pdev->dev, "IRQ eth_lpi not found\n"); } + /* For RX Channel */ + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_rx%i", i); + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -EPROBE_DEFER) + return irq; + else if (irq < 0) + break; + + stmmac_res->rx_irq[i] = irq; + } + + /* For TX Channel */ + for (i = 0; i < MTL_MAX_TX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_tx%i", i); + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -EPROBE_DEFER) + return irq; + else if (irq < 0) + break; + + stmmac_res->tx_irq[i] = irq; + } + stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0); return PTR_ERR_OR_ZERO(stmmac_res->addr); -- 2.34.1