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From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
To: Andrew Jones <ajones@ventanamicro.com>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
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	<palmer@dabbelt.com>, "paul.walmsley@sifive.com" <paul.walmsley@sifive.com>
Subject: RE: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output
 on RISC-V
Thread-Topic: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output
 on RISC-V
Thread-Index: AQHaPZHX3SCOSrSGlkOKKmkRThwdmLDLJCOA
Date: Fri, 5 Jan 2024 12:12:58 +0000
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 <20231229065405.235625-2-jeeheng.sia@starfivetech.com>
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> -----Original Message-----
> From: Andrew Jones <ajones@ventanamicro.com>
> Sent: Tuesday, January 2, 2024 11:39 PM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>
> Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; rafael=
.j.wysocki@intel.com; conor.dooley@microchip.com;
> sunilvl@ventanamicro.com; aou@eecs.berkeley.edu; palmer@dabbelt.com; paul=
.walmsley@sifive.com
> Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console out=
put on RISC-V
>=20
> On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote:
> > The ACPI SPCR code has been used to enable console output for ARM64 and
> > X86. The same code can be reused for RISC-V.
> >
> > Vendor will enable/disable the SPCR table in the firmware based on the
> > platform design. However, in cases where the SPCR table is not usable,
> > a kernel parameter could be used to specify the preferred console.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > ---
> >  arch/riscv/kernel/acpi.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> > index e619edc8b0cc..5ec2fdf9e09f 100644
> > --- a/arch/riscv/kernel/acpi.c
> > +++ b/arch/riscv/kernel/acpi.c
> > @@ -18,6 +18,7 @@
> >  #include <linux/io.h>
> >  #include <linux/memblock.h>
> >  #include <linux/pci.h>
> > +#include <linux/serial_core.h>
> >
> >  int acpi_noirq =3D 1;		/* skip ACPI IRQ initialization */
> >  int acpi_disabled =3D 1;
> > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void)
> >  		if (!param_acpi_force)
> >  			disable_acpi();
> >  	}
> > +
> > +	if (!acpi_disabled)
> > +		acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
>=20
> Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when
> acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that
> not necessary for RISC-V?
It is needed for device tree support. However, since this patch targets
ACPI, that's why I didn't include a DT solution in this patch. I can
submit a separate patch targeting DT-based earlycon if needed. Please let
me know if you think otherwise.
>=20
> Thanks,
> drew
>=20
> >  }
> >
> >  static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, =
const unsigned long end)
> > --
> > 2.34.1
> >