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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231227182727.1747435-3-Frank.Li@nxp.com> On Wed, Dec 27, 2023 at 01:27:13PM -0500, Frank Li wrote: > Refactors the phy handling logic in the imx6 PCI driver by adding > IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags. > > The drvdata::flags and a bitmask ensures a cleaner and more scalable > switch-case structure for handling phy. > > Signed-off-by: Frank Li > --- > > Notes: > Change from v4 to v5: > - none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform > require phy suppport. > > Change from v1 to v3: > - none > > drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 50d9faaa17f71..4d620249f3d52 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -60,6 +60,9 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) > #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) > +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) Every PCIe setup requires PHY for its operation. Perhaps you are referring to external PHY? If so, please rename this to IMX6_PCIE_FLAG_HAS_EXT_PHY. > + > +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > #define IMX6_PCIE_MAX_CLKS 6 > > @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) > if (ret) > return ret; > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { IMO, we would not need these kind of checks in the driver if the DT binding is properly validated using schema. But folks always want to validate "broken DT" in the drivers :( But I'm fine with this check for now since not everyone agree with above. - Mani > + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > + if (IS_ERR(imx6_pcie->phy)) > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > + "failed to get pcie phy\n"); > + } > + > switch (imx6_pcie->drvdata->variant) { > case IMX7D: > if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) > @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) > return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), > "failed to get pcie apps reset control\n"); > > - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > - if (IS_ERR(imx6_pcie->phy)) > - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > - "failed to get pcie phy\n"); > - > break; > default: > break; > @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MM] = { > .variant = IMX8MM, > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > + IMX6_PCIE_FLAG_HAS_PHY, > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > [IMX8MP] = { > .variant = IMX8MP, > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > + IMX6_PCIE_FLAG_HAS_PHY, > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MM_EP] = { > .variant = IMX8MM_EP, > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > [IMX8MP_EP] = { > .variant = IMX8MP_EP, > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்