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Date: Sat, 06 Jan 2024 15:35:58 +0000
From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "xiaochuan mao" <maoxiaochuan@loongson.cn>,
 "Huacai Chen" <chenhuacai@kernel.org>,
 "Thomas Gleixner" <tglx@linutronix.de>,
 "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
 linux-kernel@vger.kernel.org
Subject: Re: [PATCH] irqchip:Correct the offset value of interrupt status register
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=E5=9C=A82024=E5=B9=B41=E6=9C=885=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8B=E5=
=8D=881:42=EF=BC=8CXiaochuan Mao=E5=86=99=E9=81=93=EF=BC=9A
> from 2k500/2k1000 mannual known that the offset value between
> the interrupt status register and the interrupt entry register
> is 0x20.

I recall this offset is a workaround offered by Loongson staff.
INTISR0 register offered by manual is not really functional on
2K1000 MIPS

Could you please investigate with hardware folks?

Thanks
>
> Signed-off-by: Xiaochuan Mao <maoxiaochuan@loongson.cn>
> ---
>  drivers/irqchip/irq-loongson-liointc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c=20
> b/drivers/irqchip/irq-loongson-liointc.c
> index e4b33aed1c97..417b4c91ca67 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -28,7 +28,7 @@
>=20
>  #define LIOINTC_INTC_CHIP_START	0x20
>=20
> -#define LIOINTC_REG_INTC_STATUS	(LIOINTC_INTC_CHIP_START + 0x20)
> +#define LIOINTC_REG_INTC_STATUS	(LIOINTC_INTC_CHIP_START)
>  #define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
>  #define LIOINTC_REG_INTC_ENABLE	(LIOINTC_INTC_CHIP_START + 0x08)
>  #define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
> --=20
> 2.17.1

--=20
- Jiaxun