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[211.75.219.200]) by smtp.gmail.com with ESMTPSA id u13-20020a170902e80d00b001d072365b87sm3766623plg.106.2024.01.06.20.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 20:08:29 -0800 (PST) Date: Sun, 7 Jan 2024 12:08:21 +0800 From: Leo Yan To: kan.liang@linux.intel.com Cc: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, atrajeev@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V3 0/7] Clean up perf mem Message-ID: <20240107040740.GA888@debian-dev> References: <20231213195154.1085945-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231213195154.1085945-1-kan.liang@linux.intel.com> On Wed, Dec 13, 2023 at 11:51:47AM -0800, kan.liang@linux.intel.com wrote: [...] > Introduce generic functions perf_mem_events__ptr(), > perf_mem_events__name() ,and is_mem_loads_aux_event() to replace the > ARCH specific ones. > Simplify the perf_mem_event__supported(). > > Only keeps the ARCH-specific perf_mem_events array in the corresponding > mem-events.c for each ARCH. > > There is no functional change. > > The patch set touches almost all the ARCHs, Intel, AMD, ARM, Power and > etc. But I can only test it on two Intel platforms. > Please give it try, if you have machines with other ARCHs. > > Here are the test results: > Intel hybrid machine: > > $perf mem record -e list > ldlat-loads : available > ldlat-stores : available > > $perf mem record -e ldlat-loads -v --ldlat 50 > calling: record -e cpu_atom/mem-loads,ldlat=50/P -e cpu_core/mem-loads,ldlat=50/P > > $perf mem record -v > calling: record -e cpu_atom/mem-loads,ldlat=30/P -e cpu_atom/mem-stores/P -e cpu_core/mem-loads,ldlat=30/P -e cpu_core/mem-stores/P > > $perf mem record -t store -v > calling: record -e cpu_atom/mem-stores/P -e cpu_core/mem-stores/P > > > Intel SPR: > $perf mem record -e list > ldlat-loads : available > ldlat-stores : available > > $perf mem record -e ldlat-loads -v --ldlat 50 > calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=50/}:P > > $perf mem record -v > calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P -e cpu/mem-stores/P > > $perf mem record -t store -v > calling: record -e cpu/mem-stores/P After applying this series, below tests pass with Arm SPE: # ./perf c2c record -- /home/leoy/false_sharing.exe 2 # ./perf c2c report # ./perf mem record -e list # ./perf mem record -e spe-load -v --ldlat 50 # ./perf mem record -v # ./perf mem report # ./perf mem record -t store -v # ./perf mem report Tested-by: Leo Yan