Received-SPF: pass (google.com: domain of linux-kernel+bounces-19380-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
From: Minda Chen <minda.chen@starfivetech.com>
To: Conor Dooley <conor@kernel.org>,
	=?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= <kw@linux.com>,
	Rob Herring <robh+dt@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-pci@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Mason Huo <mason.huo@starfivetech.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Kevin Xie <kevin.xie@starfivetech.com>,
	Minda Chen <minda.chen@starfivetech.com>
Subject: [PATCH v14 04/22] PCI: microchip: Add bridge_addr field to struct mc_pcie
Date: Mon,  8 Jan 2024 19:05:54 +0800
Message-Id: <20240108110612.19048-5-minda.chen@starfivetech.com>
In-Reply-To: <20240108110612.19048-1-minda.chen@starfivetech.com>
References: <20240108110612.19048-1-minda.chen@starfivetech.com>
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?BJJopD0hd92xIXw1XeoVFqXZVytQ621YN99/G1hklruIsgCXu5eMeGCUyi9a?=
 =?us-ascii?Q?eVUM3G6ZgG3D+qRyqkQYe9Em/rD3WZ4oiwr3g9qfRun3khuMl6dJ7sbSUgMI?=
 =?us-ascii?Q?uBhGU4dFi7o/x+9zRTcydsVbOW2DFcOgCxJRE+5R+jZg1leIR+qeSctBy99M?=
 =?us-ascii?Q?OtI/obIbjeQvftwNt/K7+S8W+ZbvhoQhK62fCNnHa2A/M6NSCBUopEaQVeDQ?=
 =?us-ascii?Q?r/EZbtbCr3wdirlR46mOVMuMDKxuJdcM25F2FWLcqiNgePXxkfLqRlWVzMVb?=
 =?us-ascii?Q?2lEAVcKHP8pfGUHfCsaR4ofdE0V8/eV2lrxz1dvh7j6x1zjepvALYMhkJBlb?=
 =?us-ascii?Q?AR6cKg/0z4fsjI5trgWUQFER+gnX5KK6/UephwjWSP+YixCkkTIWQtTsMe4r?=
 =?us-ascii?Q?EuUyeTX/QCGC5gOljWzvrO76B/X3UMqxjRufMg6D6TT3hDusaim64YpAwj7Q?=
 =?us-ascii?Q?DP2N3wE6tJZiP4Wa6mL4F1TlicqkNQ3gqA1aXHtXDlL3kN+/tn9IlviRwyZK?=
 =?us-ascii?Q?YqBQ5+5ef0xCol18W0d2wzy5lXNJHigZdqBoW2XulVSQW+6NBJQ43/vg/emu?=
 =?us-ascii?Q?yIdIro+okXZYaqGXmOPRJjZiZnyP771z/vpIq1xC90OiqDpaxJUdxDkvREO0?=
 =?us-ascii?Q?o9SdNKJAm90PuuXRhscWm2yBfXbyjHB9eFqaOoH/2hCnKmWBYMko3gD2E3aD?=
 =?us-ascii?Q?OHxMWcd2Z2LstLiS021i20CBKtyza1mLfuJw+IC7Q7hwI+CBGTqJY+OfZHFJ?=
 =?us-ascii?Q?hlaOumgQ7VBmt761fk31jlTNNS7/FhR6L2VEgfNXzTawZLNiK56v7VKwGmEx?=
 =?us-ascii?Q?E9nEhqe4G/R6b3mQNdrQYm43AhlFhOiNcIDaVkMIkYGjQEQYixO47PCXFtK9?=
 =?us-ascii?Q?VeD176gP2IhbafWxQJG2XJdp0QpI/wqlQvbadxfrovhxXNedEsur6LFFvoFI?=
 =?us-ascii?Q?iHM+ord/14dHDo28OmmHUCz3PFcrJEuONanzIXCNyPCoOTItsvrlsLBTd4Jn?=
 =?us-ascii?Q?zty0NcAfzAK0OS4Zt5klsBt5gibbERCULMcZjlkhfSj9ywD27AVZS+X2llKz?=
 =?us-ascii?Q?YT4L6jgDYNG/WRvCMxgCvhQOp7a92ZHUHhSJ0MWgMemis4ISD/yL/fk89AM/?=
 =?us-ascii?Q?MDwFbJnTTWAvHaX1ChiDaep6uSqiqrtV7xRHVDqSsboOXnpg0lsBUkkFjysa?=
 =?us-ascii?Q?ajZObxfsUaL6MXjjQcfLdfmWGVF5UOpVed6l0q7sE4wdFcO5PZJVQDfnsNCw?=
 =?us-ascii?Q?hrzl0t0WLZKMRHIxTwUmzHyJnVU1wJCbiaWI6RiQw+h4crOh1YhLDRKucgIX?=
 =?us-ascii?Q?s2ZAYJiWZqIBIKX21GeUw/7Fn790hP96RQSiOTy3nfNpffZqgNNRTaw82LKP?=
 =?us-ascii?Q?OXxzn/J4OISUtShfHrKEsME1SgNelUe/2yEPV9SwrXjsZDMLmfj03r+3ePej?=
 =?us-ascii?Q?6OAbEy7ZIj1/46v872GJLIAyeV15w5fE5P3ivoQdC1prfMnyDdmDgMCsLhdq?=
 =?us-ascii?Q?woCUScmtYmCqtR5VQs+JRbs7uIQYYmM4zxtfMfzw8LTpnZdc8MukVMuJ0JQn?=
 =?us-ascii?Q?ZlGvChfykgIDU4bjbovIeHWjFYUnUjWPMs5PD1HmJQNNzNyaPHX2NXiTjYyc?=
 =?us-ascii?Q?DQ=3D=3D?=
X-OriginatorOrg: starfivetech.com
X-MS-Exchange-CrossTenant-Network-Message-Id: d69c881f-2a77-45d9-e1d4-08dc1039dde8
X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2024 11:06:30.3311
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 4owNnNre7KIBa3J+FQS69MsqZukZf09dBStXuzILp/AcW8MWsqn9lF2aWPrIzP96wnIU4+Oj4GCoZo1ZAQmg9wfkhOgdiGG+vwhVxk3mPA4=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0701

For bridge address base is common PLDA field, Add this to struct mc_pcie
first.

INTx and MSI codes interrupts codes will get the bridge base address from
port->bridge_addr. These codes will be changed to common codes.
axi_base_addr is Microchip its own data.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++-----------
 1 file changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
index d9030d550482..c55ede80a6d0 100644
--- a/drivers/pci/controller/plda/pcie-microchip-host.c
+++ b/drivers/pci/controller/plda/pcie-microchip-host.c
@@ -195,6 +195,7 @@ struct mc_pcie {
 	struct irq_domain *event_domain;
 	raw_spinlock_t lock;
 	struct mc_msi msi;
+	void __iomem *bridge_addr;
 };
 
 struct cause {
@@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc)
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct device *dev = port->dev;
 	struct mc_msi *msi = &port->msi;
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	unsigned long status;
 	u32 bit;
 	int ret;
@@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc)
 static void mc_msi_bottom_irq_ack(struct irq_data *data)
 {
 	struct mc_pcie *port = irq_data_get_irq_chip_data(data);
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	u32 bitpos = data->hwirq;
 
 	writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
@@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc)
 	struct mc_pcie *port = irq_desc_get_handler_data(desc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct device *dev = port->dev;
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	unsigned long status;
 	u32 bit;
 	int ret;
@@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc)
 static void mc_ack_intx_irq(struct irq_data *data)
 {
 	struct mc_pcie *port = irq_data_get_irq_chip_data(data);
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
 
 	writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
@@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data)
 static void mc_mask_intx_irq(struct irq_data *data)
 {
 	struct mc_pcie *port = irq_data_get_irq_chip_data(data);
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	unsigned long flags;
 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
 	u32 val;
@@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data)
 static void mc_unmask_intx_irq(struct irq_data *data)
 {
 	struct mc_pcie *port = irq_data_get_irq_chip_data(data);
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	unsigned long flags;
 	u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
 	u32 val;
@@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
 static int mc_pcie_setup_windows(struct platform_device *pdev,
 				 struct mc_pcie *port)
 {
-	void __iomem *bridge_base_addr =
-		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	void __iomem *bridge_base_addr = port->bridge_addr;
 	struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
 	struct resource_entry *entry;
 	u64 pci_addr;
@@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev)
 	mc_disable_interrupts(port);
 
 	bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
+	port->bridge_addr = bridge_base_addr;
 
 	/* Allow enabling MSI by disabling MSI-X */
 	val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
-- 
2.17.1