Received-SPF: pass (google.com: domain of linux-kernel+bounces-19488-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Date: Mon, 8 Jan 2024 12:21:15 +0000
From: Daniel Golle <daniel@makrotopia.org>
To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= <zajec5@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Hsin-Yi Wang <hsinyi@chromium.org>,
	=?iso-8859-1?Q?N=EDcolas_F_=2E_R_=2E_A_=2E?= Prado <nfraprado@collabora.com>,
	jason-ch chen <Jason-ch.Chen@mediatek.com>,
	Macpaul Lin <macpaul.lin@mediatek.com>,
	Bernhard =?iso-8859-1?Q?Rosenkr=E4nzer?= <bero@baylibre.com>,
	Sean Wang <sean.wang@mediatek.com>,
	Frank Wunderlich <frank-w@public-files.de>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
	=?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= <rafal@milecki.pl>
Subject: Re: [PATCH V2 3/3] arm64: dts: mediatek: mt7988: add clock
 controllers
Message-ID: <ZZvou6RXPcXZS72s@makrotopia.org>
References: <20240108085228.4727-1-zajec5@gmail.com>
 <20240108085228.4727-4-zajec5@gmail.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <20240108085228.4727-4-zajec5@gmail.com>

On Mon, Jan 08, 2024 at 09:52:28AM +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> Add bindings of on-SoC clocks.
> 
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>

Reviewed-by: Daniel Golle <daniel@makrotopia.org>

> ---
> V2: New PATCH in the series thanks to Daniel's bindings work
> 
>  arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 41 ++++++++++++++++++++++-
>  1 file changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index 5a778188ac21..bba97de4fb44 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -78,12 +78,51 @@ gic: interrupt-controller@c000000 {
>  			#interrupt-cells = <3>;
>  		};
>  
> -		watchdog@1001c000 {
> +		clock-controller@10001000 {
> +			compatible = "mediatek,mt7988-infracfg", "syscon";
> +			reg = <0 0x10001000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		clock-controller@1001b000 {
> +			compatible = "mediatek,mt7988-topckgen", "syscon";
> +			reg = <0 0x1001b000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		watchdog: watchdog@1001c000 {
>  			compatible = "mediatek,mt7988-wdt";
>  			reg = <0 0x1001c000 0 0x1000>;
>  			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
>  			#reset-cells = <1>;
>  		};
> +
> +		clock-controller@1001e000 {
> +			compatible = "mediatek,mt7988-apmixedsys";
> +			reg = <0 0x1001e000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		clock-controller@11f40000 {
> +			compatible = "mediatek,mt7988-xfi-pll";
> +			reg = <0 0x11f40000 0 0x1000>;
> +			resets = <&watchdog 16>;
> +			#clock-cells = <1>;
> +		};
> +
> +		clock-controller@15000000 {
> +			compatible = "mediatek,mt7988-ethsys", "syscon";
> +			reg = <0 0x15000000 0 0x1000>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		clock-controller@15031000 {
> +			compatible = "mediatek,mt7988-ethwarp";
> +			reg = <0 0x15031000 0 0x1000>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
>  	};
>  
>  	timer {
> -- 
> 2.35.3
>