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[178.235.179.81]) by smtp.gmail.com with ESMTPSA id bs18-20020a170906d1d200b00a2808ee8ab1sm3892978ejb.150.2024.01.08.04.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 04:32:55 -0800 (PST) From: Konrad Dybcio Date: Mon, 08 Jan 2024 13:32:31 +0100 Subject: [PATCH 14/18] clk: qcom: videocc-sm8150: Set delay for Venus CLK resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240105-topic-venus_reset-v1-14-981c7a624855@linaro.org> References: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704717148; l=851; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=vIWWe4F0QFAfFwANwsubp7EQt8hjOIin+CjR28FQWLE=; b=389KJlGYvuA+BfdullvLtbyrqDDJmucrxQl7l9ry810m5jTGduSrtabxXx2licUEVOwJZYSK7 X4b0VokWRZCC1Frf0C0nHnc7OtfKmRYHp/dEeMz5wCKdo2kVK+TB+J2 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some Venus resets may require more time when toggling. Describe that. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8150.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index f1456eaa87c4..bead5186a5d6 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -215,7 +215,7 @@ static const struct regmap_config video_cc_sm8150_regmap_config = { }; static const struct qcom_reset_map video_cc_sm8150_resets[] = { - [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 }, + [VIDEO_CC_MVSC_CORE_CLK_BCR] = { .reg = 0x850, .bit = 2, .udelay = 150 }, [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 }, [VIDEO_CC_MVS0_BCR] = { 0x870 }, [VIDEO_CC_MVS1_BCR] = { 0x8b0 }, -- 2.43.0