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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id t8-20020a056402020800b0055712dec5a6sm4367215edv.2.2024.01.08.06.22.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jan 2024 06:22:39 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 08 Jan 2024 15:22:38 +0100 Message-Id: From: "Luca Weiss" To: "Konrad Dybcio" , "Andy Gross" , "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Bhupesh Sharma" , "David Heidelberg" , "Stephan Gerhold" Cc: <~postmarketos/upstreaming@lists.sr.ht>, , "Krzysztof Kozlowski" , , , Subject: Re: [PATCH RFT] arm64: dts: qcom: sm8350: Reenable crypto & cryptobam X-Mailer: aerc 0.15.2 References: <20240108-sm8350-qce-v1-1-b7d586ff38af@fairphone.com> In-Reply-To: On Mon Jan 8, 2024 at 3:18 PM CET, Konrad Dybcio wrote: > On 8.01.2024 14:49, Luca Weiss wrote: > > When num-channels and qcom,num-ees is not provided in devicetree, the > > driver will try to read these values from the registers during probe bu= t > > this fails if the interconnect is not on and then crashes the system. > >=20 > > So we can provide these properties in devicetree (queried after patchin= g > > BAM driver to enable the necessary interconnect) so we can probe > > cryptobam without reading registers and then also use the QCE as > > expected. > > This really feels a bit backwards.. Enable the resource to query the > hardware for numbers, so that said resource can be enabled, but > slightly later :/ If you think adding interconnect support to driver and dtsi is better, let me know. Stephan (+CC) mentioned it should be okay like this *shrug* For the record, this is the same way I got the values for sc7280[0] and sm6350[1]. [0] https://lore.kernel.org/linux-arm-msm/20231229-sc7280-cryptobam-fixup-v= 1-1-bd8f68589b80@fairphone.com/ [1] https://lore.kernel.org/linux-arm-msm/20240105-sm6350-qce-v1-0-416e5c73= 19ac@fairphone.com/ diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index b46236235b7f..cd4dd9852d9e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1756,8 +1756,8 @@ cryptobam: dma-controller@1dc4000 { qcom,controlled-remotely; iommus =3D <&apps_smmu 0x594 0x0011>, <&apps_smmu 0x596 0x0011>; - /* FIXME: Probing BAM DMA causes some abort and system hang */ - status =3D "fail"; + interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "memory"; }; =20 crypto: crypto@1dfa000 { diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 5e7d332731e0..9de28f615639 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -40,6 +40,7 @@ #include #include #include +#include #include =20 #include "../dmaengine.h" @@ -394,6 +395,7 @@ struct bam_device { const struct reg_offset_data *layout; =20 struct clk *bamclk; + struct icc_path *mem_path; int irq; =20 /* dma start transaction tasklet */ @@ -1206,6 +1208,7 @@ static int bam_init(struct bam_device *bdev) bdev->num_channels =3D val & BAM_NUM_PIPES_MASK; } =20 + printk(KERN_ERR "%s:%d DBG num_ees=3D%u num_channels=3D%u\n", __func__, _= _LINE__, bdev->num_ees, bdev->num_channels); /* Reset BAM now if fully controlled locally */ if (!bdev->controlled_remotely && !bdev->powered_remotely) bam_reset(bdev); @@ -1298,6 +1301,14 @@ static int bam_dma_probe(struct platform_device *pde= v) return ret; } =20 + bdev->mem_path =3D devm_of_icc_get(bdev->dev, "memory"); + if (IS_ERR(bdev->mem_path)) + return PTR_ERR(bdev->mem_path); + + ret =3D icc_set_bw(bdev->mem_path, 1, 1); + if (ret) + return ret; + ret =3D bam_init(bdev); if (ret) goto err_disable_clk;