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[139.178.88.99]) by mx.google.com with ESMTPS id w7-20020a63f507000000b005cdacf9065fsi6105881pgh.720.2024.01.08.07.04.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 07:04:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19734-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@tq-group.com header.s=key1 header.b=AQMMH+C2; spf=pass (google.com: domain of linux-kernel+bounces-19734-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19734-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=tq-group.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id EE1A9284463 for ; Mon, 8 Jan 2024 15:04:07 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3B3E47791; Mon, 8 Jan 2024 15:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="AQMMH+C2" X-Original-To: linux-kernel@vger.kernel.org Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96EE447784; Mon, 8 Jan 2024 15:03:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1704726210; x=1736262210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lFLR9/lX88bs5FSXRG+Q/KTqO0KBNbod0EWUerJuI+M=; b=AQMMH+C2TP/ol0fPtEj2yvrfJfRiLANtNoI5zj8UgnXGjkbp0aNLYdMF lihtLB2l7qDdy8uYzmIoBksWEs3eQpl+sVz+cT/wlI7L/vkaAkkGtMVSx 5pxeFMmuhY5tMR6Oej9G8mgxzjd5jEfOBoVTuU4JtqDPAVihRf2taJS+o 89Gvy1cjFt4myvuysui6W5J1hVX6zvu9CZ30LLIfUm3IEhMaBum8uKVZT Q3tL35CvGBFkU/3x4yz+5GG2Zzj4xuDHGgq2ncMtRJjQlmrQnTdCxTWNQ nweVEvjp3gurjHKnoI3WTKyDv8Y1IRawMjQSDP8eF3Zf6UACrD0kyiWR8 w==; X-IronPort-AV: E=Sophos;i="6.04,180,1695679200"; d="scan'208";a="34789682" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 08 Jan 2024 16:03:27 +0100 Received: from steina-w.localnet (steina-w.tq-net.de [10.123.53.25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id E78F5280075; Mon, 8 Jan 2024 16:03:26 +0100 (CET) From: Alexander Stein To: dri-devel@lists.freedesktop.org Cc: Kishon Vijay Abraham I , devicetree@vger.kernel.org, Conor Dooley , Fabio Estevam , Pengutronix Kernel Team , Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, Vinod Koul , Rob Herring , NXP Linux Team , Krzysztof Kozlowski , linux-phy@lists.infradead.org, Adam Ford , linux-arm-kernel@lists.infradead.org, Adam Ford Subject: Re: [PATCH V2 2/2] phy: freescale: add Samsung HDMI PHY Date: Mon, 08 Jan 2024 16:03:26 +0100 Message-ID: <13783659.uLZWGnKmhe@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240106221907.325127-2-aford173@gmail.com> References: <20240106221907.325127-1-aford173@gmail.com> <20240106221907.325127-2-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" Hi Adam, thanks for pushing this forward. Am Samstag, 6. Januar 2024, 23:19:05 CET schrieb Adam Ford: > From: Lucas Stach >=20 > This adds the driver for the Samsung HDMI PHY found on the > i.MX8MP SoC. >=20 > Signed-off-by: Lucas Stach > Signed-off-by: Adam Ford > --- > V2: Fixed some whitespace found from checkpatch > Change error handling when enabling apbclk to use dev_err_probe > Rebase on Linux-Next >=20 > I (Adam) tried to help move this along, so I took Lucas' patch and > attempted to apply fixes based on feedback. I don't have > all the history, so apologies for that. >=20 > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index 853958fb2c06..5c2b73042dfc 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. >=20 > +config PHY_FSL_SAMSUNG_HDMI_PHY > + tristate "Samsung HDMI PHY support" > + depends on OF && HAS_IOMEM > + help > + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. > + > endif >=20 > config PHY_FSL_LYNX_28G > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makef= ile > index cedb328bc4d2..dbcafdcc8751 100644 > --- a/drivers/phy/freescale/Makefile > +++ b/drivers/phy/freescale/Makefile > @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) +=3D phy-fsl-imx8mq-usb.o > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) +=3D phy-fsl-imx8qm-lvds-phy.o > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) +=3D phy-fsl-imx8-mipi-dphy.o > obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) +=3D phy-fsl-imx8m-pcie.o > +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) +=3D phy-fsl-samsung-hdmi.o > obj-$(CONFIG_PHY_FSL_LYNX_28G) +=3D phy-fsl-lynx-28g.o I don't know if there was different feedback already. But I would have adde= d=20 the entry sorted alphabetically, thus after CONFIG_PHY_FSL_LYNX_28G. Same g= oes=20 for Kconfig as well. > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c new file mode 100644 > index 000000000000..54e93ea898f7 > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > @@ -0,0 +1,1078 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020 NXP > + * Copyright 2022 Pengutronix, Lucas Stach > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define HDMI_TX_CONTROL0 0x200 > +#define HDMI_TX_CONTROL_PHY_PWRDWN BIT(3) These defines are unused here. > + > +#define PHY_REG_33 0x84 > +#define REG33_MODE_SET_DONE BIT(7) > +#define REG33_FIX_DA BIT(1) > + > +#define PHY_REG_34 0x88 > +#define REG34_PHY_READY BIT(7) > +#define REG34_PLL_LOCK BIT(6) > +#define REG34_PHY_CLK_READY BIT(5) > + > + > +#define PHY_PLL_REGS_NUM 48 > + > +struct phy_config { > + u32 clk_rate; > + u8 regs[PHY_PLL_REGS_NUM]; Shouldn't reg be aligned along clk_rate? Despite that. Tested on TQMa8MPQL/MBa8MPxL + Full-HD HDMI monitor. Tested-by: Alexander Stein Best regards, Alexander > +}; > + > +const struct phy_config phy_pll_cfg[] =3D { > + { 22250000, { > + 0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 23750000, { > + 0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 24000000, { > + 0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 24024000, { > + 0x00, 0xD1, 0x50, 0xF1, 0x99, 0x02, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x00, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 25175000, { > + 0x00, 0xD1, 0x54, 0xFC, 0xCC, 0x91, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF5, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 25200000, { > + 0x00, 0xD1, 0x54, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 26750000, { > + 0x00, 0xD1, 0x5A, 0xF2, 0x89, 0x88, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE6, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 27000000, { > + 0x00, 0xD1, 0x5A, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 27027000, { > + 0x00, 0xD1, 0x5A, 0xF2, 0xFD, 0x0C, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 29500000, { > + 0x00, 0xD1, 0x62, 0xF4, 0x95, 0x08, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xD1, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 30750000, { > + 0x00, 0xD1, 0x66, 0xF4, 0x82, 0x01, 0x88, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC8, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 30888000, { > + 0x00, 0xD1, 0x66, 0xF4, 0x99, 0x18, 0x88, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 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0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 213000000, { > + 0x00, 0xD1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE7, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 216000000, { > + 0x00, 0xD1, 0x5A, 0x10, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 216216000, { > + 0x00, 0xD1, 0x5A, 0x12, 0xFD, 0x0C, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 237600000, { > + 0x00, 0xD1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xCF, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 254000000, { > + 0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 277500000, { > + 0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 288000000, { > + 0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 297000000, { > + 0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, > +}; > + > +struct fsl_samsung_hdmi_phy { > + struct device *dev; > + void __iomem *regs; > + struct clk *apbclk; > + struct clk *refclk; > + > + /* clk provider */ > + struct clk_hw hw; > + const struct phy_config *cur_cfg; > +}; > + > +static inline struct fsl_samsung_hdmi_phy * > +to_fsl_samsung_hdmi_phy(struct clk_hw *hw) > +{ > + return container_of(hw, struct fsl_samsung_hdmi_phy, hw); > +} > + > +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *p= hy, > + const struct phy_config=20 *cfg) > +{ > + int i, ret; > + u8 val; > + > + /* HDMI PHY init */ > + writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); > + > + for (i =3D 0; i < PHY_PLL_REGS_NUM; i++) > + writeb(cfg->regs[i], phy->regs + i * 4); > + > + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33); > + > + ret =3D readb_poll_timeout(phy->regs + PHY_REG_34, val, > + val & REG34_PLL_LOCK, > + 50, 20000); > + if (ret) > + dev_err(phy->dev, "PLL failed to lock\n"); > + > + return ret; > +} > + > +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); > + > + if (!phy->cur_cfg) > + return 74250000; > + > + return phy->cur_cfg->clk_rate; > +} > + > +static long phy_clk_round_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long=20 *parent_rate) > +{ > + int i; > + > + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) > + if (phy_pll_cfg[i].clk_rate <=3D rate) > + return phy_pll_cfg[i].clk_rate; > + > + return -EINVAL; > +} > + > +static int phy_clk_set_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long=20 parent_rate) > +{ > + struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); > + int i; > + > + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) > + if (phy_pll_cfg[i].clk_rate <=3D rate) > + break; > + > + if (i < 0) > + return -EINVAL; > + > + phy->cur_cfg =3D &phy_pll_cfg[i]; > + > + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > +} > + > +static const struct clk_ops phy_clk_ops =3D { > + .recalc_rate =3D phy_clk_recalc_rate, > + .round_rate =3D phy_clk_round_rate, > + .set_rate =3D phy_clk_set_rate, > +}; > + > +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) > +{ > + struct device *dev =3D phy->dev; > + struct device_node *np =3D dev->of_node; > + struct clk_init_data init; > + const char *parent_name; > + struct clk *phyclk; > + int ret; > + > + parent_name =3D __clk_get_name(phy->refclk); > + > + init.parent_names =3D &parent_name; > + init.num_parents =3D 1; > + init.flags =3D 0; > + init.name =3D "hdmi_pclk"; > + init.ops =3D &phy_clk_ops; > + > + phy->hw.init =3D &init; > + > + phyclk =3D devm_clk_register(dev, &phy->hw); > + if (IS_ERR(phyclk)) > + return dev_err_probe(dev, PTR_ERR(phyclk), > + "failed to register clock\n"); > + > + ret =3D of_clk_add_provider(np, of_clk_src_simple_get, phyclk); > + if (ret) > + return dev_err_probe(dev, ret, > + "failed to register clock=20 provider\n"); > + > + return 0; > +} > + > +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) > +{ > + struct fsl_samsung_hdmi_phy *phy; > + int ret; > + > + phy =3D devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); > + if (!phy) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, phy); > + phy->dev =3D &pdev->dev; > + > + phy->regs =3D devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(phy->regs)) > + return PTR_ERR(phy->regs); > + > + phy->apbclk =3D devm_clk_get(phy->dev, "apb"); > + if (IS_ERR(phy->apbclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), > + "failed to get apb clk\n"); > + > + phy->refclk =3D devm_clk_get(phy->dev, "ref"); > + if (IS_ERR(phy->refclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), > + "failed to get ref clk\n"); > + > + ret =3D clk_prepare_enable(phy->apbclk); > + if (ret) { > + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), > + "failed to enable apbclk\n"); > + } > + > + pm_runtime_get_noresume(phy->dev); > + pm_runtime_set_active(phy->dev); > + pm_runtime_enable(phy->dev); > + > + ret =3D phy_clk_register(phy); > + if (ret) { > + dev_err(&pdev->dev, "register clk failed\n"); > + goto register_clk_failed; > + } > + > + pm_runtime_put(phy->dev); > + > + return 0; > + > +register_clk_failed: > + clk_disable_unprepare(phy->apbclk); > + > + return ret; > +} > + > +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) > +{ > + of_clk_del_provider(pdev->dev.of_node); > + > + return 0; > +} > + > +#ifdef CONFIG_PM > +static int fsl_samsung_hdmi_phy_suspend(struct device *dev) > +{ > + struct fsl_samsung_hdmi_phy *phy =3D dev_get_drvdata(dev); > + > + clk_disable_unprepare(phy->apbclk); > + > + return 0; > +} > + > +static int fsl_samsung_hdmi_phy_resume(struct device *dev) > +{ > + struct fsl_samsung_hdmi_phy *phy =3D dev_get_drvdata(dev); > + int ret =3D 0; > + > + ret =3D clk_prepare_enable(phy->apbclk); > + if (ret) { > + dev_err(phy->dev, "failed to enable apbclk\n"); > + return ret; > + } > + > + if (phy->cur_cfg) > + ret =3D fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > + > + return ret; > + > +} > +#endif > + > +static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops =3D { > + SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend, > + fsl_samsung_hdmi_phy_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > + > +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] =3D { > + { > + .compatible =3D "fsl,imx8mp-hdmi-phy", > + }, { > + /* sentinel */ > + } > +}; > +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); > + > +static struct platform_driver fsl_samsung_hdmi_phy_driver =3D { > + .probe =3D fsl_samsung_hdmi_phy_probe, > + .remove =3D fsl_samsung_hdmi_phy_remove, > + .driver =3D { > + .name =3D "fsl-samsung-hdmi-phy", > + .of_match_table =3D fsl_samsung_hdmi_phy_of_match, > + .pm =3D &fsl_samsung_hdmi_phy_pm_ops, > + }, > +}; > +module_platform_driver(fsl_samsung_hdmi_phy_driver); > + > +MODULE_AUTHOR("Sandor Yu "); > +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); > +MODULE_LICENSE("GPL v2"); =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/