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Mon, 08 Jan 2024 09:45:31 -0800 (PST) Received: from google.com ([2620:15c:9d:2:7a4a:2478:1813:e8c2]) by smtp.gmail.com with ESMTPSA id q1-20020a170902bd8100b001d06b63bb98sm176997pls.71.2024.01.08.09.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 09:45:31 -0800 (PST) Date: Mon, 8 Jan 2024 09:45:28 -0800 From: 'Dmitry Torokhov' To: David Laight Cc: Arnd Bergmann , "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Linus Torvalds Subject: Re: [PATCH] asm-generic: make sparse happy with odd-sized put_unaligned_*() Message-ID: References: <12d88da48f6947ab86a845e8d02319ff@AcuMS.aculab.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12d88da48f6947ab86a845e8d02319ff@AcuMS.aculab.com> On Mon, Jan 08, 2024 at 11:03:22AM +0000, David Laight wrote: > From: Dmitry Torokhov > > Sent: 08 January 2024 06:17 > > > > __put_unaligned_be24() and friends use implicit casts to convert > > larger-sized data to bytes, which trips sparse truncation warnings when > > the argument is a constant: > > > > CC [M] drivers/input/touchscreen/hynitron_cstxxx.o > > CHECK drivers/input/touchscreen/hynitron_cstxxx.c > > drivers/input/touchscreen/hynitron_cstxxx.c: note: in included file (through > > arch/x86/include/generated/asm/unaligned.h): > > ./include/asm-generic/unaligned.h:119:16: warning: cast truncates bits from constant value (aa01a0 > > becomes a0) > > ./include/asm-generic/unaligned.h:120:20: warning: cast truncates bits from constant value (aa01 > > becomes 1) > > ./include/asm-generic/unaligned.h:119:16: warning: cast truncates bits from constant value (ab00d0 > > becomes d0) > > ./include/asm-generic/unaligned.h:120:20: warning: cast truncates bits from constant value (ab00 > > becomes 0) > > > > To avoid this let's mask off upper bits explicitly, the resulting code > > should be exactly the same, but it will keep sparse happy. > > Maybe someone should fix sparse? I proposed doing this in https://lore.kernel.org/oe-kbuild-all/ZZnzd3s2L-ZwGOlz@google.com/ but the idea was not welcome. > I have seen a compiler generate two explicit masks with 0xff > followed by a byte write for: > *p = (char)(x & 0xff); > but I expect modern gcc is ok. > > > Reported-by: kernel test robot > > Suggested-by: Linus Torvalds > > Closes: https://lore.kernel.org/oe-kbuild-all/202401070147.gqwVulOn-lkp@intel.com/ > > Signed-off-by: Dmitry Torokhov > > --- > > include/asm-generic/unaligned.h | 24 ++++++++++++------------ > > 1 file changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h > > index 699650f81970..a84c64e5f11e 100644 > > --- a/include/asm-generic/unaligned.h > > +++ b/include/asm-generic/unaligned.h > > @@ -104,9 +104,9 @@ static inline u32 get_unaligned_le24(const void *p) > > > > static inline void __put_unaligned_be24(const u32 val, u8 *p) > > { > > - *p++ = val >> 16; > > - *p++ = val >> 8; > > - *p++ = val; > > + *p++ = (val >> 16) & 0xff; > > + *p++ = (val >> 8) & 0xff; > > + *p++ = val & 0xff; > > } > > What happens if you implement the as (eg): > *p = val >> 16; > put_unaligned_be16(p + 1, val); > I think that should generate better code. > And it may stop sparse bleating. This is rarely in a hot path (typically you do this with a "slow" device), and while being faster it looks more complex. But if that's what people prefer... Thanks. -- Dmitry