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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR12MB7199.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6260edd7-7234-4fc7-11b1-08dc11081401 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2024 11:42:37.2597 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SBA1ywaK3kAmlpFfND6MOBuCRtLUYVuCQzWPVAc0MUSQqTmJkkYjjWkShUvZBbRveEr6FCgJOWsTNSBcvO/1RQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8328 I am working to get the code changes suggested in this thread to get=0A= to the next version.=0A= =0A= Moreover based on the other design related comments for BAR approach=0A= and support for the enable/disable bit, comments follow.=0A= =0A= > There are a lot of VMMs and OSs this needs to support so it must all=0A= > be consistent. For better or worse the decision was taken for the vPCI=0A= > spec to use BAR not ACPI, in part due to feedback from the broader VMM=0A= > ecosystem, and informed by future product plans.=0A= > =0A= > So, if vfio does special regions then qemu and everyone else has to=0A= > fix it to meet the spec.=0A= =0A= Ack, I'm putting this into the commit log as a reason to go with the BAR=0A= approach for future reference.=0A= =0A= >>> I'd suggest we take a look at whether we need to continue to pursue=0A= >>> honoring the memory enable bit for these BARs and make a conscious and= =0A= >>> documented decision if we choose to ignore it.=0A= >>=0A= >> Let's document it.=0A= > Ok, I'd certainly appreciate more background around why it was chosen=0A= > to expose the device differently than bare metal in the commit log and=0A= > code comments and in particular why we're consciously choosing not to=0A= > honor these specific PCI semantics. Presumably we'd remove the -EIO=0A= > from the r/w path based on the memory enable state as well.=0A= =0A= Ack, will add to the commit log and remove EIO.=0A= =0A= >> unprogrammed BARs are ignored (ie. not exposed to userspace), so perhaps= =0A= >> as long as it can be guaranteed that an access with the address space=0A= >> enable bit cleared cannot generate a system level fault, we actually=0A= >> have no strong argument to strictly enforce the address space bits.=0A= >=0A= > This is what I think, yes.=0A= =0A= Ack, so given the access does not cause system level fault, I'll not enforc= e=0A= the enable/disable bit. Though I'll put this information in the commit log= =0A= for reference as well and the reason for this choice.=