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From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 9 Jan 2024 13:42:53 +0100
Message-ID: <CACRpkdZMkyJdkFt_x-6iubLZ-KzewvmT0zi4HAas0Xy9DpPn3g@mail.gmail.com>
Subject: Re: [DO NOT MERGE v6 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
To: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: linux-sh@vger.kernel.org, Damien Le Moal <dlemoal@kernel.org>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Geert Uytterhoeven <geert+renesas@glider.be>, Michael Turquette <mturquette@baylibre.com>, 
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Hi Yoshinori,

thanks for your patch!

On Tue, Jan 9, 2024 at 9:24=E2=80=AFAM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:

> Renesas SH7751 PCI Controller json-schema.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
(...)
> +  renesas,bus-arbit-round-robin:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set DMA bus arbitration to round robin.
> +
> +  pci-command-reg-fast-back-to-back:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI command register Fast Back-to-Back enable bit.
> +
> +  pci-command-reg-serr:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI command register SERR# enable.
> +
> +  pci-command-reg-wait-cycle-control:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI command register Wait cycle control bit.
> +
> +  pci-command-reg-parity-error-response:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register Parity error response bit.
> +
> +  pci-command-reg-vga-snoop:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register VGA palette snoop bit.
> +
> +  pci-command-reg-write-invalidate:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register Memory write and invaldate enable bit=
.
> +
> +  pci-command-reg-special-cycle:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register Special cycle bit.
> +
> +  pci-command-reg-bus-master:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register Bus master bit.
> +
> +  pci-command-reg-memory-space:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register Memory space bit.
> +
> +  pci-command-reg-io-space:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      Set for PCI Command register I/O space bit.

Do you really need to configure all these things? It seems they are
just set to default values anyway?

Can't you just look at the compatible "renesas,sh7751-pci" and
set it to the values you know are needed for that compatible?

> +  pci-bar:
> +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +    description: Overwrite to  PCI CONFIG Base Address Registers value.
> +    items:
> +      items:
> +        - description: BAR register number
> +        - description: BAR register value
> +    minItems: 1
> +    maxItems: 6

Same with this, isn't this always the same (hardcoded) values
for "renesas,sh7751-pci" if used?

> +            interrupt-map =3D <0x0000 0 0 1 &julianintc 5>,
> +                            <0x0000 0 0 2 &julianintc 6>,
> +                            <0x0000 0 0 3 &julianintc 7>,
> +                            <0x0000 0 0 4 &julianintc 8>,
> +                            <0x0800 0 0 1 &julianintc 6>,
> +                            <0x0800 0 0 2 &julianintc 7>,
> +                            <0x0800 0 0 3 &julianintc 8>,
> +                            <0x0800 0 0 4 &julianintc 5>,
> +                            <0x1000 0 0 1 &julianintc 7>,
> +                            <0x1000 0 0 2 &julianintc 8>,
> +                            <0x1000 0 0 3 &julianintc 5>,
> +                            <0x1000 0 0 4 &julianintc 6>;

This interrupt-map looks very strange, usually the last cell is the polarit=
y
flag and here it is omitted? I would expect something like:

<0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, (...)

The interrupt-map schema in dtschema isn't really looking at this
so it is easy to get it wrong.

Yours,
Linus Walleij