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Date: Tue, 9 Jan 2024 15:01:33 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: MD Danish Anwar <danishanwar@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Tero Kristo <kristo@kernel.org>, srk@ti.com, r-gunasekaran@ti.com,
	afd@ti.com
Subject: Re: [PATCH v2 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet
 support
Message-ID: <70f2b16c-19af-41af-bd7f-255814899477@lunn.ch>
References: <20231212165832.3933335-1-danishanwar@ti.com>
 <20231212165832.3933335-3-danishanwar@ti.com>
 <1a2aba0c-5c4d-4258-b89c-b1be4593d7ff@lunn.ch>
 <f7dd0868-1eda-4dff-9b9f-ae55f07c7d96@ti.com>
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On Tue, Jan 09, 2024 at 10:53:16AM +0530, MD Danish Anwar wrote:
> Hi Andrew,
> 
> On 13/12/23 6:56 pm, Andrew Lunn wrote:
> > On Tue, Dec 12, 2023 at 10:28:31PM +0530, MD Danish Anwar wrote:
> >> ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded.
> >>
> >> The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares
> >> MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to
> >> CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO
> >> bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2)
> >> port is kept disable and ICSSG1 is enabled in single MAC mode by
> >> default.
> > 
> > FYI
> > 
> > I want to review all this MII muxing, but it won't be today.
> 
> Did you get the chance to review this?

Sorry, no.

I will try to find some time in the next two weeks. During the merge
window it tends to be quieter.

       Andrew