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Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , Teoh Ji Sheng Subject: RE: [PATCH net-next v2 3/4] net: stmmac: Add support for TX/RX channel interrupt Thread-Topic: [PATCH net-next v2 3/4] net: stmmac: Add support for TX/RX channel interrupt Thread-Index: AQHaP6Y7sC4xQVBFpEuN3if/vsfTLLDO07kAgAO85HA= Date: Wed, 10 Jan 2024 05:45:17 +0000 Message-ID: References: <20240105070925.2948871-1-leong.ching.swee@intel.com> <20240105070925.2948871-4-leong.ching.swee@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CH0PR11MB5490:EE_|BL1PR11MB5239:EE_ x-ms-office365-filtering-correlation-id: 408e0935-fc0d-4d7e-4c43-08dc119f5319 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH0PR11MB5490.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 408e0935-fc0d-4d7e-4c43-08dc119f5319 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jan 2024 05:45:17.0823 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TA5TeHYesHAjLYgeaifiWVatp5P3sq6jpHrkBNnwhYM3PHQNF5EvKPugx4e9IKgUZmQeTiEefaM7UFYql40vBIwEzWYIchv1ar6Mn0FKXgI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5239 X-OriginatorOrg: intel.com > -----Original Message----- > From: Serge Semin > Sent: Monday, January 8, 2024 4:39 AM > To: Swee, Leong Ching > Cc: Maxime Coquelin ; Alexandre Torgue > ; Jose Abreu ; > David S . Miller ; Eric Dumazet > ; Jakub Kicinski ; Paolo Abeni > ; Rob Herring ; Krzysztof > Kozlowski ; Conor Dooley > ; Giuseppe Cavallaro ; > linux-stm32@st-md-mailman.stormreply.com; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > netdev@vger.kernel.org; devicetree@vger.kernel.org; Teoh Ji Sheng > > Subject: Re: [PATCH net-next v2 3/4] net: stmmac: Add support for TX/RX > channel interrupt >=20 > On Fri, Jan 05, 2024 at 03:09:24PM +0800, Leong Ching Swee wrote: > > From: Swee Leong Ching > > > > Enable TX/RX channel interrupt registration for MAC that interrupts > > CPU through shared peripheral interrupt (SPI). > > > > Per channel interrupts and interrupt-names are registered through, > > Eg: 4 tx and 4 rx channels: > > interrupts =3D , > > , > > , > > ; > > ; > > ; > > ; > > ; interrupt-names =3D > > "dma_tx0", > > "dma_tx1", > > "dma_tx2", > > "dma_tx3", > > "dma_rx0", > > "dma_rx1", > > "dma_rx2", > > "dma_rx3"; > > > > Signed-off-by: Teoh Ji Sheng > > Signed-off-by: Swee Leong Ching > > --- > > .../ethernet/stmicro/stmmac/stmmac_platform.c | 28 > > +++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > > b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > > index 70eadc83ca68..ae6859153e98 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > > @@ -710,6 +710,10 @@ > EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt); > > int stmmac_get_platform_resources(struct platform_device *pdev, > > struct stmmac_resources *stmmac_res) { >=20 > > + char irq_name[9]; > > + int i; > > + int irq; > > + >=20 > Reverse xmas tree please. Also what the point in having "i" and "irq" > defined separately? Wouldn't it be better to merge them into a single > statement: > + char irq_name[9]; > + int i, irq; > Will rework this in v3. > > memset(stmmac_res, 0, sizeof(*stmmac_res)); > > > > /* Get IRQ information early to have an ability to ask for deferred > > @@ -743,6 +747,30 @@ int stmmac_get_platform_resources(struct > platform_device *pdev, > > dev_info(&pdev->dev, "IRQ eth_lpi not found\n"); > > } > > >=20 > > + /* For RX Channel */ >=20 > Why haven't you added a more descriptive comment as I suggested on v1: >=20 > + /* Get optional Tx/Rx DMA per-channel IRQs, which otherwise > + * are supposed to be delivered via the common MAC IRQ line > + */ >=20 > ? >=20 Sorry I missed this, will rework this on v3. > > + for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) { > > + snprintf(irq_name, sizeof(irq_name), "dma_rx%i", i); > > + irq =3D platform_get_irq_byname_optional(pdev, irq_name); > > + if (irq =3D=3D -EPROBE_DEFER) > > + return irq; > > + else if (irq < 0) > > + break; > > + > > + stmmac_res->rx_irq[i] =3D irq; > > + } > > + >=20 > > + /* For TX Channel */ >=20 > * see the comment above >=20 > -Serge(y) >=20 > > + for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { > > + snprintf(irq_name, sizeof(irq_name), "dma_tx%i", i); > > + irq =3D platform_get_irq_byname_optional(pdev, irq_name); > > + if (irq =3D=3D -EPROBE_DEFER) > > + return irq; > > + else if (irq < 0) > > + break; > > + > > + stmmac_res->tx_irq[i] =3D irq; > > + } > > + > > stmmac_res->addr =3D devm_platform_ioremap_resource(pdev, 0); > > > > return PTR_ERR_OR_ZERO(stmmac_res->addr); > > -- > > 2.34.1 > > > >