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Message-ID: <a242202d-c576-05e8-8726-91dfdbe10e7b@quicinc.com>
Date: Wed, 10 Jan 2024 16:01:06 +0530
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Subject: Re: [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on
 SM8150
Content-Language: en-US
To: Stephen Boyd <sboyd@kernel.org>, Bjorn Andersson <andersson@kernel.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Deepak Katragadda
	<dkatraga@codeaurora.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette
	<mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>, Taniya Das
	<quic_tdas@quicinc.com>,
        Vinod Koul <vkoul@kernel.org>
CC: <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        Ajit Pandey
	<quic_ajipan@quicinc.com>,
        Imran Shaik <quic_imrashai@quicinc.com>,
        "Jagadeesh Kona" <quic_jkona@quicinc.com>
References: <20240104-sm8150-dfs-support-v1-0-a5eebfdc1b12@quicinc.com>
 <20240104-sm8150-dfs-support-v1-1-a5eebfdc1b12@quicinc.com>
 <988ae72846dc680382f98b63b61a8c32.sboyd@kernel.org>
From: "Satya Priya Kakitapalli (Temp)" <quic_skakitap@quicinc.com>
In-Reply-To: <988ae72846dc680382f98b63b61a8c32.sboyd@kernel.org>
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On 1/5/2024 3:06 AM, Stephen Boyd wrote:
> Quoting Satya Priya Kakitapalli (2024-01-04 06:23:04)
>> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
>> index 05d115c52dfe..6d76fd344ddf 100644
>> --- a/drivers/clk/qcom/gcc-sm8150.c
>> +++ b/drivers/clk/qcom/gcc-sm8150.c
>> @@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>>          { }
>>   };
>>   
>> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> Can these be const?


We update the ops inside the qcom_cc_register_rcg_dfs. Hence cannot make 
this as const.


>> +       .name = "gcc_qupv3_wrap0_s0_clk_src",
>> +       .parent_data = gcc_parents_0,
>> +       .num_parents = ARRAY_SIZE(gcc_parents_0),
>> +       .flags = CLK_SET_RATE_PARENT,
>> +       .ops = &clk_rcg2_ops,
>> +};
>> +
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>>          .cmd_rcgr = 0x17148,
>>          .mnd_width = 16,
>>          .hid_width = 5,
>>          .parent_map = gcc_parent_map_0,
>>          .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> -       .clkr.hw.init = &(struct clk_init_data){
>> -               .name = "gcc_qupv3_wrap0_s0_clk_src",
> [...]
>> @@ -3786,6 +3850,13 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
>>          regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
>>          regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>>   
>> +       ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> +                                      ARRAY_SIZE(gcc_dfs_clocks));
>> +       if (ret) {
>> +               dev_err(&pdev->dev, "Failed to register with DFS!\n");
> Use
>
> 		return dev_err_probe(...);


Okay.