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Date: Wed, 10 Jan 2024 12:57:54 +0100
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Subject: Re: [PATCH 5/6] arm64: dts: qcom: ipq5332: Add RDP441 board device
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To: Luo Jie <quic_luoj@quicinc.com>, andersson@kernel.org,
 konrad.dybcio@linaro.org, robh+dt@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
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References: <20240110112059.2498-1-quic_luoj@quicinc.com>
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <20240110112059.2498-6-quic_luoj@quicinc.com>
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On 10/01/2024 12:20, Luo Jie wrote:
> From: Lei Wei <quic_leiwei@quicinc.com>
> 
> RDP441 board has onboard QCA8386 switch and 10G SFP port.
> 
> Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> index 846413817e9a..d51968e9d601 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> @@ -12,6 +12,15 @@
>  / {
>  	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
>  	compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
> +
> +	soc@0 {

Nope, DTS does not define soc nodes.

> +		sfp1: sfp-1 {

Why is this soc? Where is the MMIO address?

> +			compatible = "sff,sfp";
> +			i2c-bus = <&blsp1_i2c1>;
> +			los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
> +			tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
>  };
>  
>  &blsp1_i2c1 {
> @@ -63,3 +72,45 @@ data-pins {
>  		};
>  	};
>  };
> +
> +&qcom_ppe {
> +	qcom,port_phyinfo {

Eh... We talk now about basics: please don't post downstream code, but
first clean it up from all the junk. All the basic issues which you have
in downstream and which we do not accept upstream.

I do not believe that this code passed internal review.

NAK.

Best regards,
Krzysztof