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Date: Wed, 10 Jan 2024 18:28:19 +0530
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Subject: Re: [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance
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To: Viresh Kumar <viresh.kumar@linaro.org>
CC: Bjorn Helgaas <helgaas@kernel.org>, <agross@kernel.org>,
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From: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
In-Reply-To: <20240110073807.sqwmsyr6nmigg6zc@vireshk-i7>
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On 1/10/2024 1:08 PM, Viresh Kumar wrote:
> On 10-01-24, 12:42, Krishna Chaitanya Chundru wrote:
>> At present we are not changing the link width after link is initialized, but
>> we have plans to
>>
>> add support change link width dynamically at runtime.
> Hmm okay.
>
>> So, I think it is better to have ICC BW voting in the driver itself.
> I guess it is better to have more entries in the OPP table then.. 15-20 OPPs
> isn't too many to be honest.
>
> Replicating code is the last thing I would like to do.
>
> Maybe you can show the different layouts of the OPP table if you are concerned.
> We can then see if it is getting too much or not.

Viresh,

it might be less only for now may be around 20 opp entries, but PCIe 
spec is being updated every few years and a new gen

gen speed will release, right now PCIe GEN6 is released but I don't we 
had any device in the market now and GEN7 is in process.

So in future it might become very big table. Either we need to come up 
with a framework in the OPP to select the BW based up on lane width

for particular speed or use the driver way.


Thanks & Regards,

Krishna Chaitanya.