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Message-ID: <c62db276-289e-4a21-8e2f-6a6055e7c4ca@redhat.com>
Date: Thu, 11 Jan 2024 11:16:56 +0100
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Subject: Re: [PATCH v2 1/2] usb: dwc3: host: Set XHCI_SG_TRB_CACHE_SIZE_QUIRK
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To: Prashanth K <quic_prashk@quicinc.com>,
 Thinh Nguyen <Thinh.Nguyen@synopsys.com>,
 Mathias Nyman <mathias.nyman@intel.com>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
 stable@vger.kernel.org
References: <20231212112521.3774610-1-quic_prashk@quicinc.com>
 <20231212112521.3774610-2-quic_prashk@quicinc.com>
From: Hans de Goede <hdegoede@redhat.com>
In-Reply-To: <20231212112521.3774610-2-quic_prashk@quicinc.com>
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Hi,

On 12/12/23 12:25, Prashanth K wrote:
> Upstream commit bac1ec551434 ("usb: xhci: Set quirk for
> XHCI_SG_TRB_CACHE_SIZE_QUIRK") introduced a new quirk in XHCI
> which fixes XHC timeout, which was seen on synopsys XHCs while
> using SG buffers. But the support for this quirk isn't present
> in the DWC3 layer.
> 
> We will encounter this XHCI timeout/hung issue if we run iperf
> loopback tests using RTL8156 ethernet adaptor on DWC3 targets
> with scatter-gather enabled. This gets resolved after enabling
> the XHCI_SG_TRB_CACHE_SIZE_QUIRK. This patch enables it using
> the xhci device property since its needed for DWC3 controller.
> 
> In Synopsys DWC3 databook,
> Table 9-3: xHCI Debug Capability Limitations
> Chained TRBs greater than TRB cache size: The debug capability
> driver must not create a multi-TRB TD that describes smaller
> than a 1K packet that spreads across 8 or more TRBs on either
> the IN TR or the OUT TR.
> 
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
> ---
>  drivers/usb/dwc3/host.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
> index 61f57fe5bb78..31a496233d87 100644
> --- a/drivers/usb/dwc3/host.c
> +++ b/drivers/usb/dwc3/host.c
> @@ -89,6 +89,8 @@ int dwc3_host_init(struct dwc3 *dwc)
>  
>  	memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
>  
> +	props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk");
> +

If you do this you also need to make the props array 1 entry bigger (increase
it from 4 to 5 entries). Before this patch there are max 3 properties added
and there needs to be an empty terminating property at the end (which
is what the memset is for). So before this patch props[] needs to have
4 entries (which it does) and thus after this patch props[] needs to
have 5 entire.s

Regards,

Hans