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b=XX6Xq46lj6+JMZhj6js+g5PDfCkrYBVq7zvkxDeScOkEnIYiCdAOFTEzxofC8sfV09JtM6gBvifuWH99YX4L24HFN8GL5386EDGyJpmnP+G9TkuK/HxjCe9Pe/TVV5v6JgMUTCFwU0IeP/ivXFWEw3uA1rXIIt9DOMj68KiQRnw= Received: from DM6PR12MB3993.namprd12.prod.outlook.com (2603:10b6:5:1c5::29) by IA0PR12MB7530.namprd12.prod.outlook.com (2603:10b6:208:440::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Thu, 11 Jan 2024 12:13:13 +0000 Received: from DM6PR12MB3993.namprd12.prod.outlook.com ([fe80::b46:e1e6:ac2a:4386]) by DM6PR12MB3993.namprd12.prod.outlook.com ([fe80::b46:e1e6:ac2a:4386%7]) with mapi id 15.20.7159.020; Thu, 11 Jan 2024 12:13:13 +0000 From: "Manne, Nava kishore" To: Xu Yilun CC: "mdf@kernel.org" , "hao.wu@intel.com" , "yilun.xu@intel.com" , "trix@redhat.com" , "peter.colberg@intel.com" , "conor.dooley@microchip.com" , "v.georgiev@metrotek.ru" , "Simek, Michal" , Marco Pagani , "gregkh@linuxfoundation.org" , "ruanjinjie@huawei.com" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "git (AMD-Xilinx)" Subject: RE: [RFC] FPGA Subsystem User Space Interface Proposal Thread-Topic: [RFC] FPGA Subsystem User Space Interface Proposal Thread-Index: Ado+yABjPiRB0KySRY6DC56HOLfe9ADNGpkAAKKugUA= Date: Thu, 11 Jan 2024 12:13:12 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3993.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7411a3d-9f7b-464d-5e60-08dc129eaf06 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jan 2024 12:13:12.9887 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vPxorPavcv6SM0GFPPA65FUfavzR7XVkGH2BuZTq3Zr1b2JPI7RHqnN9GGKRQc9d X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7530 Hi Yilun, Please find my response inline. > -----Original Message----- > From: Xu Yilun > Sent: Monday, January 8, 2024 12:02 PM > To: Manne, Nava kishore > Cc: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com; > trix@redhat.com; peter.colberg@intel.com; conor.dooley@microchip.com; > v.georgiev@metrotek.ru; Simek, Michal ; Marco > Pagani ; gregkh@linuxfoundation.org; > ruanjinjie@huawei.com; linux-fpga@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; git (AMD-Xi= linx) > > Subject: Re: [RFC] FPGA Subsystem User Space Interface Proposal >=20 > On Thu, Jan 04, 2024 at 04:52:15AM +0000, Manne, Nava kishore wrote: > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D > > | Introduction | > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D This document provides a detailed overview of the proposed Kernel > > feature for FPGA Manager subsystem user interface. > > It describes the problem statement behind the proposal, the problem to = be > solved, a top-level solution design. > > > > Table of Contents: > > ------------------ > > A. Problem Statement and Background > > B. Scope and Out of scope of the proposal > > B.1 Scope > > B.2 Out of scope > > C. Proposed Solution > > D. Proposed User Interface Details > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D > > | A. Problem Statement and Background = | > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D The existing FPGA manager subsystem didn't have any user space > > interface (other than the status/state in sysfs) in Kernel. > > Basically, FPGAs are semiconductor devices that can be reprogrammed for > desired hardware functionality. > > FPGAs can be reprogrammed at runtime with different types of logic and = IPs > as per user need and hence there is a need to use device tree overlays fo= r > removing/updating/adding the devices at runtime for the IPs/controllers t= hat > are present in FPGA. > > But we don't have any user interface in kernel for updating the device = tree > at runtime. > > > > Sometime back there was a series sent by Pantelis Antoniou > (https://lore.kernel.org/lkml/1414528565-10907-4-git-send-email- > pantelis.antoniou@konsulko.com/). > > This patch introduced a user interface configfs for Device Tree overlay= s, a > method of dynamically altering the kernel's live Device Tree. However, t= his > patch series was not accepted in mainline due to various concerns. > > For more details refer to this link: > > > https://elinux.org/Frank%27s_Evolving_Overlay_Thoughts#issues_and_what > > _needs_to_be_completed_--_Not_an_exhaustive_list > > > > One of the major valid concerns that were raised with this configfs int= erface > was security as it opens up the interface to users for modifying the live= device > tree. > > > > So, in order to configure/program the FPGA devices, All the major > > vendors of FPGA are using this configfs series as out-of-tree patch for > configuring the FPGAs and there was never an attempt to introduce a gener= ic > interface to configure/program the FPGA in upstream and hence upstream > kernel ended up in not having proper support for FPGAs. > > > > The proposal below tries to address this gap of FPGA programmability by > providing an interface to the user. > > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D > > | B. Proposed Solution | > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D > > =3D The proposed interface adds a new sysfs interface (of-fpga-region.c= ) > > as part of the fpga subsystem and it is responsible for supporting the = below > functionalities. >=20 > Why only for of-fpga-region? There are also FPGA regions that don't rely = on > OF. My quick idea is that an interface for /sys/class/fpga-region/ and OF= could > be one of the implementation. >=20 I agree, few devices(Like - dfl-fme-region.c) are rely only on FPGA region = and they are not using OF. Thanks for pointing out this case. I will look at the possibility of having a generic interface for both Fpga = region and OF and I will get back to you soon. Regards, Navakishore.