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Subject: Re: [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation
From: patchwork-bot+linux-riscv@kernel.org
Message-Id: 
 <170498463792.20080.16092078813919262282.git-patchwork-notify@kernel.org>
Date: Thu, 11 Jan 2024 14:50:37 +0000
References: <20231227175739.1453782-1-samuel.holland@sifive.com>
In-Reply-To: <20231227175739.1453782-1-samuel.holland@sifive.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, aou@eecs.berkeley.edu, conor@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
 paul.walmsley@sifive.com, robh+dt@kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Wed, 27 Dec 2023 09:57:38 -0800 you wrote:
> The current description implies that only a single address translation
> mode is available to the operating system. However, some implementations
> support multiple address translation modes, and the operating system is
> free to choose between them.
> 
> Per the RISC-V privileged specification, Sv48 implementations must also
> implement Sv39, and likewise Sv57 implies support for Sv48. This means
> it is possible to describe all supported address translation modes using
> a single value, by naming the largest supported mode. This appears to
> have been the intended usage of the property, so note it explicitly.
> 
> [...]

Here is the summary with links:
  - dt-bindings: riscv: cpus: Clarify mmu-type interpretation
    https://git.kernel.org/riscv/c/b4070c2a242e

You are awesome, thank you!
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