Received-SPF: pass (google.com: domain of linux-kernel+bounces-23823-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Message-ID: <e893c298-fbfa-4ae4-9b76-72a5030a5530@quicinc.com>
Date: Thu, 11 Jan 2024 23:59:59 +0800
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 3/6] arm64: dts: qcom: ipq5332: Add MDIO device tree
Content-Language: en-US
To: Andrew Lunn <andrew@lunn.ch>
CC: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>,
        <quic_kkumarcs@quicinc.com>, <quic_suruchia@quicinc.com>,
        <quic_soni@quicinc.com>, <quic_pavir@quicinc.com>,
        <quic_souravp@quicinc.com>, <quic_linchen@quicinc.com>,
        <quic_leiwei@quicinc.com>
References: <20240110112059.2498-1-quic_luoj@quicinc.com>
 <20240110112059.2498-4-quic_luoj@quicinc.com>
 <4bc0aff5-8a1c-44a6-89d8-460961a61310@lunn.ch>
From: Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <4bc0aff5-8a1c-44a6-89d8-460961a61310@lunn.ch>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit


On 1/10/2024 9:35 PM, Andrew Lunn wrote:
> On Wed, Jan 10, 2024 at 07:20:56PM +0800, Luo Jie wrote:
>> Add the MDIO device tree of ipq5332.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 44 +++++++++++++++++++++++++++
>>   1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index bc89480820cb..e6c780e69d6e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -214,6 +214,38 @@ serial_0_pins: serial0-state {
>>   				drive-strength = <8>;
>>   				bias-pull-up;
>>   			};
>> +
>> +			mdio0_pins: mdio0-state {
>> +				mux_0 {
>> +					pins = "gpio25";
>> +					function = "mdc0";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +				};
>> +
>> +				mux_1 {
>> +					pins = "gpio26";
>> +					function = "mdio0";
>> +					drive-strength = <8>;
>> +					bias-pull-up;
>> +				};
>> +			};
>> +
>> +			mdio1_pins: mdio1-state {
>> +				mux_0 {
>> +					pins = "gpio27";
>> +					function = "mdc1";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +				};
>> +
>> +				mux_1 {
>> +					pins = "gpio28";
>> +					function = "mdio1";
>> +					drive-strength = <8>;
>> +					bias-pull-up;
>> +				};
> 
> I don't know why i'm asking this, because i don't really expect a
> usable answer. What sort of MUX is this? Should you be using one of
> the muxes in drivers/net/mdio/mdio-mux-* or something similar?
> 
>      Andrew

Sorry for the confusion, the pin nodes are for the MDIO and MDC, these
PINs are used by the dedicated hardware MDIO block in the SoC. I will 
update the node name from mux_0 to MDC, mux_1 to MDIO, to make it clear. 
The driver for this node is drivers/net/mdio/mdio-ipq4019.c, it is not 
related to the mdio-mux-* code.