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Date: Thu, 11 Jan 2024 08:17:51 -0800
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Subject: Re: [PATCH] x86/cpu: Add a VMX flag to enumerate 5-level EPT support
 to userspace
From: Sean Christopherson <seanjc@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, 
	Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org, kvm@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Yi Lai <yi1.lai@intel.com>, 
	Tao Su <tao1.su@linux.intel.com>, Xudong Hao <xudong.hao@intel.com>
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On Thu, Jan 11, 2024, Paolo Bonzini wrote:
> On Wed, Jan 10, 2024 at 1:23=E2=80=AFAM Sean Christopherson <seanjc@googl=
e.com> wrote:
> > Add a VMX flag in /proc/cpuinfo, ept_5level, so that userspace can quer=
y
> > whether or not the CPU supports 5-level EPT paging.
>=20
> I think this is a good idea independent of the selftests issue.
>=20
> For selftests, we could get similar info from the feature MSR
> mechanism, i.e. KVM_GET_MSRS(MSR_IA32_VMX_EPT_VPID_CAP), but only on
> Intel and only if nested virtualization is enabled, so that's
> inferior.
>=20
> A better idea for selftests is to add a new KVM_CAP_PHYS_ADDR_SIZE,
> which could be implemented by all architectures and especially by both
> x86 vendors.

Doh.  I was thinking this wouldn't be a problem on AMD, but a guest can gen=
erate
52-bit GPAs even without LA57.

> However, I am not sure for example if different VM types (read: TDX?) cou=
ld
> have different maximum physical addresses, and that would have to be take=
n
> into consideration when designing the API.