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From: Paolo Bonzini <pbonzini@redhat.com>
Date: Thu, 11 Jan 2024 21:02:18 +0100
Message-ID: <CABgObfaByKFKRtLpY1yAJFmcY1WxWcn3tpeVw7Nho+qk0PFUbQ@mail.gmail.com>
Subject: Re: [PATCH] x86/cpu: Add a VMX flag to enumerate 5-level EPT support
 to userspace
To: Sean Christopherson <seanjc@google.com>
Cc: Tao Su <tao1.su@linux.intel.com>, Chao Gao <chao.gao@intel.com>, 
	Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, 
	Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org, kvm@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Yi Lai <yi1.lai@intel.com>, 
	Xudong Hao <xudong.hao@intel.com>
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On Thu, Jan 11, 2024 at 5:25=E2=80=AFPM Sean Christopherson <seanjc@google.=
com> wrote:
> > It is unusual to assign a huge RAM to guest, but passthrough a device a=
lso may trigger
> > this issue which we have met, i.e. alloc memslot for the 64bit BAR whic=
h can set
> > bits[51:48]. BIOS can control the BAR address, e.g. seabios moved 64bit=
 pci window
> > to end of address space by using advertised physical bits[1].
>
> Drat.  Do you know if these CPUs are going to be productized?  We'll stil=
l need
> something in KVM either way, but whether or not the problems are more or =
less
> limited to funky software setups might influence how we address this.

Wait, we do have an API for guest physical address size. It's
KVM_GET_SUPPORTED_CPUID2: the # of bits is in leaf 0x80000008, bits
0:7 of EAX. In fact that leaf is what firmware uses to place the BARs.
So it just needs to be adjusted for VMX in __do_cpuid_func, and looked
up in selftests.

Paolo