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Fri, 12 Jan 2024 15:00:43 GMT Received: from [10.253.78.164] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 12 Jan 2024 07:00:38 -0800 Message-ID: <840fc48b-956d-47e8-8307-c419afb1efc2@quicinc.com> Date: Fri, 12 Jan 2024 23:00:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] Add PPE device tree node for Qualcomm IPQ SoC Content-Language: en-US To: Krzysztof Kozlowski , , , , , CC: , , , , , , , , , , References: <20240110112059.2498-1-quic_luoj@quicinc.com> <458ded82-b200-4946-9b22-31cda68f1c8c@linaro.org> From: Jie Luo In-Reply-To: <458ded82-b200-4946-9b22-31cda68f1c8c@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GDThB25HhrPiZt1J6QblhAeyuRjVe6HS X-Proofpoint-GUID: GDThB25HhrPiZt1J6QblhAeyuRjVe6HS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=532 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401120117 On 1/10/2024 8:13 PM, Krzysztof Kozlowski wrote: > On 10/01/2024 12:20, Luo Jie wrote: >> The PPE(packet process engine) hardware block is supported by Qualcomm >> IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various >> packet processing modules such as the routing and bridging flow engines, >> L2 switch capability, VLAN and tunnels. Also included are integrated >> ethernet MAC and PCS(uniphy), which is used to connect with the external >> PHY devices by PCS. >> >> This patch series enables support for the following DTSI functionality >> for Qualcomm IPQ9574 and IPQ5332 chipsets. >> >> 1. Add PPE (Packet Processing Engine) HW support >> >> 2. Add IPQ9574 RDP433 board support, where the PPE is connected >> with qca8075 PHY and AQ PHY. >> >> 3. Add IPQ5332 RDP441 board support, where the PPE is connected >> with qca8386 and SFP >> >> PPE DTS depends on the NSSCC clock driver below, which provides the >> clocks for the PPE driver. > > DTS cannot depend on clock drivers. Maybe you meant that it depends on > NSSCC clock controller DTS changes, which would be fine. However > depending on drivers is neither necessary nor allowed. > > Best regards, > Krzysztof > Yes, this DTSI series depends on the NSSCC clock controller DTS patches which are referred to in the cover letter. I will rectify the cover letter text when the series resumes later.