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Date: Fri, 12 Jan 2024 17:05:08 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Luo Jie <quic_luoj@quicinc.com>, andersson@kernel.org,
 konrad.dybcio@linaro.org, robh+dt@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
CC: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
 quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_soni@quicinc.com,
 quic_pavir@quicinc.com, quic_souravp@quicinc.com, quic_linchen@quicinc.com,
 quic_leiwei@quicinc.com
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_6/6=5D_arm64=3A_dts=3A_qcom=3A_i?= =?US-ASCII?Q?pq9574=3A_Add_RDP433_board_device_tree?=
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On 10 January 2024 13:20:59 EET, Luo Jie <quic_luoj@quicinc=2Ecom> wrote:
>From: Lei Wei <quic_leiwei@quicinc=2Ecom>
>
>RDP433 board has four QCA8075 PHYs and two Aquantia 10G PHY onboard=2E
>
>Signed-off-by: Lei Wei <quic_leiwei@quicinc=2Ecom>
>Signed-off-by: Luo Jie <quic_luoj@quicinc=2Ecom>
>---
> arch/arm64/boot/dts/qcom/ipq9574-rdp433=2Edts | 66 +++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433=2Edts b/arch/arm64/b=
oot/dts/qcom/ipq9574-rdp433=2Edts
>index 1bb8d96c9a82=2E=2E298c0853b4d2 100644
>--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433=2Edts
>+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433=2Edts
>@@ -60,3 +60,69 @@ rclk-pins {
> 		};
> 	};
> };
>+
>+&qcom_ppe {
>+	qcom,port_phyinfo {
>+		ppe_port0: port@0 {
>+			port_id =3D <1>;
>+			phy-mode =3D "qsgmii";
>+			phy-handle =3D <&phy0>;
>+		};
>+		ppe_port1: port@1 {
>+			port_id =3D <2>;
>+			phy-mode =3D "qsgmii";
>+			phy-handle =3D <&phy1>;
>+		};
>+		ppe_port2: port@2 {
>+			port_id =3D <3>;
>+			phy-mode =3D "qsgmii";
>+			phy-handle =3D <&phy2>;
>+		};
>+		ppe_port3: port@3 {
>+			port_id =3D <4>;
>+			phy-mode =3D "qsgmii";
>+			phy-handle =3D <&phy3>;
>+		};
>+		ppe_port4: port@4 {
>+			port_id =3D <5>;
>+			phy-mode =3D "usxgmii";
>+			phy-handle =3D <&phy4>;
>+		};
>+		ppe_port5: port@5 {
>+			port_id =3D <6>;
>+			phy-mode =3D "usxgmii";
>+			phy-handle =3D <&phy5>;
>+		};
>+	};
>+};
>+
>+&mdio {
>+	reset-gpios =3D <&tlmm 60 GPIO_ACTIVE_LOW>;
>+	status =3D "okay";
>+
>+	phy0: ethernet-phy@0 {
>+		      reg =3D <16>;
>+	      };

This part looks extremely wrong to me=2E If the reg is 16, then it should =
be @16 as well=2E You should have got a warning here=2E

>+
>+	phy1: ethernet-phy@1 {
>+		      reg =3D <17>;
>+	      };
>+
>+	phy2: ethernet-phy@2 {
>+		      reg =3D <18>;
>+	      };
>+
>+	phy3: ethernet-phy@3 {
>+		      reg =3D <19>;
>+	      };
>+
>+	phy4: ethernet-phy@4 {
>+		      compatible =3D"ethernet-phy-ieee802=2E3-c45";
>+		      reg =3D <8>;
>+	      };
>+
>+	phy5: ethernet-phy@5 {
>+		      compatible =3D"ethernet-phy-ieee802=2E3-c45";
>+		      reg =3D <0>;
>+	      };
>+};