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charset=us-ascii Content-Disposition: inline Hi Linus, There was a last minute doubt from Intel on their error handling plan. They decided to remove it since it has uAPI meaning this was delayed while they made that edit. The prior verions has been in linux-next for a while now but the update has only had a day. This PR includes the second part of the nested translation items for iommufd, details in the tag. For those following, these series are still progressing: - User page table invalidation (non-Intel) has a roadmap: https://lore.kernel.org/linux-iommu/20231209014726.GA2945299@nvidia.com/ There will be at least two more invalidation IOCTLs - IOMMU_DEVICE_INVALIDATE and IOMMU_VIOMMU_INVALIDATE in future. - ARM SMMUv3 nested translation: https://github.com/jgunthorpe/linux/commits/smmuv3_newapi - Draft AMD IOMMU nested translation: https://lore.kernel.org/linux-iommu/20240112000646.98001-1-suravee.suthikulpanit@amd.com - ARM SMMUv3 Dirty tracking: https://lore.kernel.org/linux-iommu/20231128094940.1344-1-shameerali.kolothum.thodi@huawei.com/ - x86 KVM and IOMMU page table sharing (IOMMU_DOMAIN_KVM): https://lore.kernel.org/all/20231202091211.13376-1-yan.y.zhao@intel.com/ There is also a lot of ongoing work to consistently and generically enable PASID and SVA support in all the IOMMU drivers: SMMUv3: https://lore.kernel.org/r/0-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com https://lore.kernel.org/r/0-v3-9083a9368a5c+23fb-smmuv3_newapi_p2_jgg@nvidia.com AMD: https://lore.kernel.org/linux-iommu/20231212085224.6985-1-vasant.hegde@amd.com/ https://lore.kernel.org/linux-iommu/20231221111558.64652-1-vasant.hegde@amd.com/ Intel: https://lore.kernel.org/r/20231017032045.114868-1-tina.zhang@intel.com RFC patches for PASID support in iommufd & vfio: https://lore.kernel.org/all/20231127063428.127436-1-yi.l.liu@intel.com/ https://lore.kernel.org/all/20231127063909.129153-1-yi.l.liu@intel.com/ IO page faults and events delivered to userspace through iommufd: https://lore.kernel.org/all/20231220012332.168188-1-baolu.lu@linux.intel.com/ https://lore.kernel.org/all/20231026024930.382898-1-baolu.lu@linux.intel.com/ RFC patches exploring support for the first Intel Scalable IO Virtualization (SIOV r1) device are posted: https://lore.kernel.org/all/20231009085123.463179-1-yi.l.liu@intel.com/ A lot of the iommufd support has now been merged to qemu, though I think we are still needing dirty tracking and nesting stuff. https://lore.kernel.org/all/20231121084426.1286987-1-zhenzhong.duan@intel.com/ https://lore.kernel.org/all/20230622214845.3980-1-joao.m.martins@oracle.com/ A video of the iommufd session at LPC has been posted: https://youtu.be/IE_A8wSWV7g Thanks, Jason The following changes since commit 861deac3b092f37b2c5e6871732f3e11486f7082: Linux 6.7-rc7 (2023-12-23 16:25:56 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git tags/for-linus-iommufd for you to fetch changes up to 47f2bd2ff382e5fe766b1322e354558a8da4a470: iommufd/selftest: Check the bus type during probe (2024-01-11 15:53:28 -0400) ---------------------------------------------------------------- iommufd for 6.8 This brings the first of three planned user IO page table invalidation operations: - IOMMU_HWPT_INVALIDATE allows invalidating the IOTLB integrated into the iommu itself. The Intel implementation will also generate an ATC invalidation to flush the device IOTLB as it unambiguously knows the device, but other HW will not. It goes along with the prior PR to implement userspace IO page tables (aka nested translation for VMs) to allow Intel to have full functionality for simple cases. An Intel implementation of the operation is provided. Fix a small bug in the selftest mock iommu driver probe. ---------------------------------------------------------------- Jason Gunthorpe (1): iommufd/selftest: Check the bus type during probe Lu Baolu (2): iommu: Add cache_invalidate_user op iommu/vt-d: Add iotlb flush for nested domain Nicolin Chen (4): iommu: Add iommu_copy_struct_from_user_array helper iommufd/selftest: Add mock_domain_cache_invalidate_user support iommufd/selftest: Add IOMMU_TEST_OP_MD_CHECK_IOTLB test op iommufd/selftest: Add coverage for IOMMU_HWPT_INVALIDATE ioctl Yi Liu (2): iommufd: Add IOMMU_HWPT_INVALIDATE iommufd: Add data structure for Intel VT-d stage-1 cache invalidation drivers/iommu/intel/nested.c | 88 +++++++++++++++ drivers/iommu/iommufd/hw_pagetable.c | 41 +++++++ drivers/iommu/iommufd/iommufd_private.h | 10 ++ drivers/iommu/iommufd/iommufd_test.h | 23 ++++ drivers/iommu/iommufd/main.c | 3 + drivers/iommu/iommufd/selftest.c | 104 +++++++++++++++--- include/linux/iommu.h | 77 +++++++++++++ include/uapi/linux/iommufd.h | 79 +++++++++++++ tools/testing/selftests/iommu/iommufd.c | 152 ++++++++++++++++++++++++++ tools/testing/selftests/iommu/iommufd_utils.h | 55 ++++++++++ 10 files changed, 619 insertions(+), 13 deletions(-) --Z4b8nnA/cAQCd4Ug Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRRRCHOFoQz/8F5bUaFwuHvBreFYQUCZaF7pwAKCRCFwuHvBreF YX3yAP0bCfw55km2i2uu5mAhuZK2r0J5+VlSgb6BW3+POQfdlgEA/cecY2rTJjpw u2hc5n+e2+p7OkqV37yWh4zVGm8OfAE= =PF9p -----END PGP SIGNATURE----- --Z4b8nnA/cAQCd4Ug--