Received-SPF: pass (google.com: domain of linux-kernel+bounces-26933-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1;
From: "Duan, Zhenzhong" <zhenzhong.duan@intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, "joro@8bytes.org" <joro@8bytes.org>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>, "jgg@nvidia.com"
	<jgg@nvidia.com>, "Tian, Kevin" <kevin.tian@intel.com>,
	"robin.murphy@arm.com" <robin.murphy@arm.com>, "baolu.lu@linux.intel.com"
	<baolu.lu@linux.intel.com>
CC: "cohuck@redhat.com" <cohuck@redhat.com>, "eric.auger@redhat.com"
	<eric.auger@redhat.com>, "nicolinc@nvidia.com" <nicolinc@nvidia.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>, "mjrosato@linux.ibm.com"
	<mjrosato@linux.ibm.com>, "chao.p.peng@linux.intel.com"
	<chao.p.peng@linux.intel.com>, "yi.y.sun@linux.intel.com"
	<yi.y.sun@linux.intel.com>, "peterx@redhat.com" <peterx@redhat.com>,
	"jasowang@redhat.com" <jasowang@redhat.com>,
	"shameerali.kolothum.thodi@huawei.com"
	<shameerali.kolothum.thodi@huawei.com>, "lulu@redhat.com" <lulu@redhat.com>,
	"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>,
	"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-kselftest@vger.kernel.org" <linux-kselftest@vger.kernel.org>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>, "Zeng, Xin"
	<xin.zeng@intel.com>, "Zhao, Yan Y" <yan.y.zhao@intel.com>,
	"j.granados@samsung.com" <j.granados@samsung.com>,
	"binbin.wu@linux.intel.com" <binbin.wu@linux.intel.com>
Subject: RE: [PATCH v11 0/8] Add iommufd nesting (part 2/2)
Thread-Topic: [PATCH v11 0/8] Add iommufd nesting (part 2/2)
Thread-Index: AQHaREQgjuYqviKNs0qU7NFykhF/jLDbxwug
Date: Tue, 16 Jan 2024 03:03:42 +0000
Message-ID: <SJ0PR11MB6744D35289BAA619D9A1584892732@SJ0PR11MB6744.namprd11.prod.outlook.com>
References: <20240111041015.47920-1-yi.l.liu@intel.com>
In-Reply-To: <20240111041015.47920-1-yi.l.liu@intel.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?M47nbl8sv7VZDYN3A6EZRH4QVqwV9lZenxh7wCGV0BCFL6P23zAfHo9ppcIB?=
 =?us-ascii?Q?atbG6xWq6KjWSfK7vMUQBLWW3BtPfkSxVKSsoeWQhYWJG980w4OJuaS5khe6?=
 =?us-ascii?Q?2VDOAroOdvKWH3jvgXihWUpeKsAJVf9NhzKnTHM9Lc0eHsYqKpIu77pBB2T3?=
 =?us-ascii?Q?mtu1klpiHVCB5qdOEcUc+4ludP53QXE9QRbP1ih4rD7RK40uLi5rFjeF2dPj?=
 =?us-ascii?Q?/OrohxnkFb559op0G5fjR5kuxB+2nmG3XT9fbNu1j0lhguowcLc+RItaT2ey?=
 =?us-ascii?Q?TR8YMoSsbVxcI84wyX+9+mFVW+6yhd+TJvmlpoonFmUAlWoGR/xx9d8/16i5?=
 =?us-ascii?Q?MixZQ6XZ7B+cr2hTdaULng52YuCbaSifMiCT2DxTtH3y1ORKswoMp/z0rDB5?=
 =?us-ascii?Q?Ew624aLySLPV8Pq97JZPVD4Jb6nBHRllzFt4Fe3vZdELaGvKFmKBRI5gHcSU?=
 =?us-ascii?Q?Wkle4XATWGqzN4pg2UBOR7LgHZHtkgdkzJ7VvUn/bZMps3DiSZBXhdwsRY7W?=
 =?us-ascii?Q?WWNadIo35QdwpnfddO+bUoN/6IOEM8qYhXJuAHaYWC8KOQJCRD5SwjRGpXKg?=
 =?us-ascii?Q?e1f11ojTipqyENaYcz1AIoqVm+LlvRPYnZTjRfU5faErZJyvMy4Yn5wJnEp6?=
 =?us-ascii?Q?JsK/932wMC0X1rHdjFUJq2K9pJoBmblM0h7g7mNrXXopzH9zgeU6TkcehHDL?=
 =?us-ascii?Q?Ob8/GAOzXs6ZCFWhCe5mQJY0gkrZOOiCJyY33yEufnZI36gY6voOw4xaMj0W?=
 =?us-ascii?Q?OswzEGwge8riqbbum5YFaz/Ddtlnp705ZuvG37+98+hhrCdbWYnejRV7yA2m?=
 =?us-ascii?Q?8R6wr4GL99P1sxhtSDFNTxXeTdrCZUmMeWwjgtO4aEfKxhsAjbkN7J3AQB0b?=
 =?us-ascii?Q?9eTJYUmZJ1Kx11ibR56Gtmtxl1UnnLKNZ4UR6fmqNMAMxHZFjdO8TF1mTA5n?=
 =?us-ascii?Q?1Tq9xF+mbkEDbcqFXNttvYe/Q2/beGjLBNQP2g2tjb8J0xFrs6o26mvgw/Id?=
 =?us-ascii?Q?X12jpVLnYTk80YfqT6hPGgQVCpg3W50VOwIZOnMQgOtAsWdYU/wbueFAnlNn?=
 =?us-ascii?Q?4Gdc709uIJoTCdc+db9HBd6g8aiHE8Nc1CzzmgYgHdeoOlQ/ByA4CWGnYCDz?=
 =?us-ascii?Q?hjtMOteBkad1xse/vhJKD+U/C0bvQBqi7BA/t3QlYl+0E97pZ18R6fWMMWSy?=
 =?us-ascii?Q?j5gaIltaSyjPfM8a17jFJsvimWRCsqEAGNBh48VSdJHnrgfvpV+rlffRQ3eG?=
 =?us-ascii?Q?LfgsVpAm+AOZbQmJyVR3dWzGv1uIUnYY2fOIL9XBXdDFpBVKykHGkWXX+z7b?=
 =?us-ascii?Q?9yychxAX3J2L247YInkN5RnOLe1zroNaarRCmkugBh2yjx04F0/V6dSVizFp?=
 =?us-ascii?Q?6/c2Qx2VPH0+ZxVLy/XvTeqylNbLsT5lzObXjYcplZF2WbxP5MSLXHB21SDw?=
 =?us-ascii?Q?yCnY8eGhCd1xha9ZLSCmKxZ6ue2zEHgQj3gD3X6JtF7LAdmFfkvInkjKkqqM?=
 =?us-ascii?Q?JOLiFJ+wgyURsPwwZFt0cembwkQ4SqALZuCMb4Y5bL40ZKlDOkQx0u5GVeXG?=
 =?us-ascii?Q?MDJ2zubkqJO1lrq0d9OMCCz8pd1By069C8q3z2+8?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: SJ0PR11MB6744.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 3390522c-ad84-4086-ee36-08dc163fbee2
X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Jan 2024 03:03:42.0615
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: wXNR9RfR9w8Pb9waF6x7eiFfa9wknQMTGmCDV7TeLuTwVuA5c6BV9V6vQGcLxI/wji+XoEjzruI/hqyvKEl0Orj+boboJ1p5rX4t3y3UEKs=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR11MB6708
X-OriginatorOrg: intel.com


>-----Original Message-----
>From: Liu, Yi L <yi.l.liu@intel.com>
>Subject: [PATCH v11 0/8] Add iommufd nesting (part 2/2)
>
>Nested translation is a hardware feature that is supported by many modern
>IOMMU hardwares. It has two stages (stage-1, stage-2) address translation
>to get access to the physical address. stage-1 translation table is owned
>by userspace (e.g. by a guest OS), while stage-2 is owned by kernel. Chang=
es
>to stage-1 translation table should be followed by an IOTLB invalidation.
>
>Take Intel VT-d as an example, the stage-1 translation table is I/O page
>table. As the below diagram shows, guest I/O page table pointer in GPA
>(guest physical address) is passed to host and be used to perform the stag=
e-
>1
>address translation. Along with it, modifications to present mappings in t=
he
>guest I/O page table should be followed with an IOTLB invalidation.
>
>    .-------------.  .---------------------------.
>    |   vIOMMU    |  | Guest I/O page table      |
>    |             |  '---------------------------'
>    .----------------/
>    | PASID Entry |--- PASID cache flush --+
>    '-------------'                        |
>    |             |                        V
>    |             |           I/O page table pointer in GPA
>    '-------------'
>Guest
>------| Shadow |---------------------------|--------
>      v        v                           v
>Host
>    .-------------.  .------------------------.
>    |   pIOMMU    |  |  FS for GIOVA->GPA     |
>    |             |  '------------------------'
>    .----------------/  |
>    | PASID Entry |     V (Nested xlate)
>    '----------------\.----------------------------------.
>    |             |   | SS for GPA->HPA, unmanaged domain|
>    |             |   '----------------------------------'
>    '-------------'
>Where:
> - FS =3D First stage page tables
> - SS =3D Second stage page tables
><Intel VT-d Nested translation>
>
>This series is based on the first part which was merged [1], this series i=
s to
>add the cache invalidation interface or the userspace to invalidate cache
>after
>modifying the stage-1 page table. This includes both the iommufd changes
>and the
>VT-d driver changes.
>
>Complete code can be found in [2], QEMU could can be found in [3].
>
>At last, this is a team work together with Nicolin Chen, Lu Baolu. Thanks
>them for the help. ^_^. Look forward to your feedbacks.
>
>[1] https://lore.kernel.org/linux-iommu/20231026044216.64964-1-
>yi.l.liu@intel.com/ - merged
>[2] https://github.com/yiliu1765/iommufd/tree/iommufd_nesting
>[3]
>https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_nesting
>_rfcv1

This series is tested with a real implementation of QEMU at
https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html

May be late, but still

Tested-by: Zhenzhong Duan <zhenzhong.duan@intel.com>

Thanks
Zhenzhong