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Subject: Re: [PATCH v2] irqchip/loongson-eiointc: Refine irq affinity setting
 during resume
To: Sergey Shtylyov <s.shtylyov@omp.ru>, Huacai Chen <chenhuacai@kernel.org>,
 Jiaxun Yang <jiaxun.yang@flygoat.com>, Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
 lvjianmin@loongson.cn
References: <20240116080555.409215-1-maobibo@loongson.cn>
 <58b05897-8d06-52fa-8cde-ca7caa591200@omp.ru>
From: maobibo <maobibo@loongson.cn>
Message-ID: <236c62f1-29b9-bbd2-1391-bb713d9cd3c8@loongson.cn>
Date: Tue, 16 Jan 2024 16:26:34 +0800
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Sergey,

Thanks for reviewing my patch.
I reply inline.

On 2024/1/16 下午4:17, Sergey Shtylyov wrote:
> On 1/16/24 11:05 AM, Bibo Mao wrote:
> 
>> During suspend and resume, other CPUs are hot-unpluged and IRQs are
>> migrated to CPU0. So it is not necessary to restore irq affinity for
>> eiointc irq controller.
>>
>> Also there is some optimization for the interrupt dispatch function
>> eiointc_irq_dispatch. There are 256 IRQs supported for eiointc, eiointc
>> irq handler reads the bitmap and find pending irqs when irq happens.
>> So there are four times of consecutive iocsr_read64 operations for the
>> total 256 bits to find all pending irqs. If the pending bitmap is zero,
>> it means that there is no pending irq for the this irq bitmap range,
>> we can skip handling to avoid some useless operations sush as clearing
> 
>      s/sush/such/?
will fix.

> 
>> hw ISR.
> 
>     This sounds like you need 2 patches to deal with 2 separate issues...
Sure, I will separate it into 2 patches in next version.

Regards
Bibo Mao
> 
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> [...]
> 
> MBR, Sergey
>