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References: <20240116113939.17339-1-othacehe@gnu.org> <20240116113939.17339-3-othacehe@gnu.org>
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From: Fabio Estevam <festevam@gmail.com>
Date: Tue, 16 Jan 2024 11:07:22 -0300
Message-ID: <CAOMZO5CsJzQNsW2wgSU6HxE0kVczXBFdZUdGgsMp1xTVPh2-zA@mail.gmail.com>
Subject: Re: [PATCH 2/2] arm64: dts: imx93-phycore-segin: Add Phytec i.MX93 Segin
To: Mathieu Othacehe <othacehe@gnu.org>
Cc: Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, 
	Pengutronix Kernel Team <kernel@pengutronix.de>, NXP Linux Team <linux-imx@nxp.com>, Li Yang <leoyang.li@nxp.com>, 
	Stefan Wahren <wahrenst@gmx.net>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org
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On Tue, Jan 16, 2024 at 8:39=E2=80=AFAM Mathieu Othacehe <othacehe@gnu.org>=
 wrote:

> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts=
/freescale/Makefile
> index 2e027675d7bb..6cb6d9f8783e 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb
>  dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb
> +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phycore-segin.dtb

Please keep this in alphabetical order.

> +#include "imx93-phycore-som.dtsi"
> +
> +/{
> +       model =3D "PHYTEC phyBOARD-Segin-i.MX93";
> +       compatible =3D "phytec,imx93-phycore-segin",
> +                    "phytec,imx93-phycore-som", "fsl,imx93";

Can't the compatible be in a single line?

> +       model =3D "PHYTEC phyCORE-i.MX93";
> +       compatible =3D "phytec,imx93-phycore-som", "fsl,imx93";
> +
> +       reserved-memory {
> +               ranges;
> +               #address-cells =3D <2>;
> +               #size-cells =3D <2>;

Is this needed?

> +&iomuxc {
> +       pinctrl_usdhc1: usdhc1grp {
> +               fsl,pins =3D <
> +                       MX93_PAD_SD1_CLK__USDHC1_CLK            0x15fe
> +                       MX93_PAD_SD1_CMD__USDHC1_CMD            0x13fe
> +                       MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x13fe
> +                       MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x13fe
> +                       MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x13fe
> +                       MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x13fe
> +                       MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x13fe
> +                       MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x13fe
> +                       MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x13fe
> +                       MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x13fe
> +                       MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x15fe
> +               >;
> +       };
> +

Please remove this blank line.
> +};