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bh=8mVrgl5xMNMm3WZOrIWhZNDZHloqaD1XFaFbuzdsviM=; b=cfY2OqOCFRcI1e3AOkEb5pDgSI iYgrk6FIHj2duCg0p3VQP/3DuAf5Ocz273VHzNCGbmWA585dW9wPwlj4i8fBGqzcClfUnP2C1Zdid LFfgC8uRLttGJjLtHzwCab7cyze7pd+Kw/7RoHf6HpN1iKia0rjV+CVnwdR0auZstPoo=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1rPsMW-005MUt-Sm; Tue, 16 Jan 2024 23:56:52 +0100 Date: Tue, 16 Jan 2024 23:56:52 +0100 From: Andrew Lunn To: Jie Luo Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_soni@quicinc.com, quic_pavir@quicinc.com, quic_souravp@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com Subject: Re: [PATCH 3/6] arm64: dts: qcom: ipq5332: Add MDIO device tree Message-ID: <6975e79a-67eb-46d7-8445-92610b8b5198@lunn.ch> References: <20240110112059.2498-1-quic_luoj@quicinc.com> <20240110112059.2498-4-quic_luoj@quicinc.com> <4bc0aff5-8a1c-44a6-89d8-460961a61310@lunn.ch> <61973012-3f74-4b58-9575-3bc5199f61d9@lunn.ch> <5c88945b-4a80-4346-a77c-82a68ae02047@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5c88945b-4a80-4346-a77c-82a68ae02047@quicinc.com> > Another one is the MDIO slave(gpio25, 26), which is dedicated > for receiving the back pressure signal from the connected Ethernet switch > device QCA8386. > > There is a MDIO master block integrated in QCA8386 switch device, this > integrated MDIO master is dedicated for generating the back > pressure signal to IPQ5332 SoC. > > This MDIO slave block of IPQ5322 just needs to configure these PIN > mux for MDC and MDIO PINs. No additional driver is needed for this MDIO > slave block of IPQ5332. So there is a proprietary protocol running over the MDIO bus? And its completely implemented in hardware in the slave block? Is this even MDIO? Does it use c22 or c45 bus transactions? How is the slave address configured, or is that also hard coded? Andrew