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Date: Wed, 17 Jan 2024 12:00:39 +0530
From: Manivannan Sadhasivam <mani@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to
 dedicated schema
Message-ID: <20240117063039.GA8708@thinkpad>
References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org>
 <20240108-dt-bindings-pci-qcom-split-v1-1-d541f05f4de0@linaro.org>
 <20240116144419.GA3856889-robh@kernel.org>
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In-Reply-To: <20240116144419.GA3856889-robh@kernel.org>

On Tue, Jan 16, 2024 at 08:44:19AM -0600, Rob Herring wrote:
> On Mon, Jan 08, 2024 at 03:19:14PM +0100, Krzysztof Kozlowski wrote:
> > The qcom,pcie.yaml binding file containing all possible Qualcomm SoC
> > PCIe root complexes gets quite complicated with numerous if:then:
> > conditions customizing clocks, interrupts, regs and resets.  Adding and
> > reviewing new devices is difficult, so simplify it by having shared
> > common binding and file with only one group of compatible devices:
> > 
> > 1. Copy all common qcom,pcie.yaml properties (so everything except
> >    supplies) to a new shared qcom,pcie-common.yaml schema.
> > 2. Move SM8550 PCIe compatible devices to dedicated binding file.
> > 
> > This creates equivalent SM8550 schema file, except missing required
> > compatible which is actually redundant.
> > 
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > ---
> >  .../devicetree/bindings/pci/qcom,pcie-common.yaml  |  98 ++++++++++++
> >  .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml  | 171 +++++++++++++++++++++
> >  .../devicetree/bindings/pci/qcom,pcie.yaml         |  38 -----
> >  3 files changed, 269 insertions(+), 38 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> > new file mode 100644
> > index 000000000000..125136176f93
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm PCI Express Root Complex Common Properties
> > +
> > +maintainers:
> > +  - Bjorn Andersson <andersson@kernel.org>
> > +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > +
> > +properties:
> > +  reg:
> > +    minItems: 4
> > +    maxItems: 6
> > +
> > +  reg-names:
> > +    minItems: 4
> > +    maxItems: 6
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 8
> > +
> > +  interrupt-names:
> > +    minItems: 1
> > +    maxItems: 8
> > +
> > +  iommu-map:
> > +    minItems: 1
> > +    maxItems: 16
> > +
> > +  clocks:
> > +    minItems: 3
> > +    maxItems: 13
> > +
> > +  clock-names:
> > +    minItems: 3
> > +    maxItems: 13
> > +
> > +  dma-coherent: true
> > +
> > +  interconnects:
> > +    maxItems: 2
> > +
> > +  interconnect-names:
> > +    items:
> > +      - const: pcie-mem
> > +      - const: cpu-pcie
> > +
> > +  phys:
> > +    maxItems: 1
> > +
> > +  phy-names:
> > +    items:
> > +      - const: pciephy
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    minItems: 1
> > +    maxItems: 12
> > +
> > +  reset-names:
> > +    minItems: 1
> > +    maxItems: 12
> > +
> > +  perst-gpios:
> > +    description: GPIO controlled connection to PERST# signal
> > +    maxItems: 1
> > +
> > +  wake-gpios:
> > +    description: GPIO controlled connection to WAKE# signal
> > +    maxItems: 1
> > +
> > +required:
> > +  - reg
> > +  - reg-names
> > +  - interrupt-map-mask
> > +  - interrupt-map
> > +  - clocks
> > +  - clock-names
> > +
> > +anyOf:
> > +  - required:
> > +      - interrupts
> > +      - interrupt-names
> > +      - "#interrupt-cells"
> > +  - required:
> > +      - msi-map
> > +      - msi-map-mask
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +additionalProperties: true
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> > new file mode 100644
> > index 000000000000..b6d025f153bc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> > @@ -0,0 +1,171 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM8550 PCI Express Root Complex
> > +
> > +maintainers:
> > +  - Bjorn Andersson <andersson@kernel.org>
> > +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > +
> > +description:
> > +  Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
> > +  the Synopsys DesignWare PCIe IP.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - const: qcom,pcie-sm8550
> > +      - items:
> > +          - enum:
> > +              - qcom,pcie-sm8650
> > +          - const: qcom,pcie-sm8550
> > +
> > +  reg:
> > +    minItems: 5
> > +    maxItems: 6
> > +
> > +  reg-names:
> > +    minItems: 5
> > +    items:
> > +      - const: parf # Qualcomm specific registers
> > +      - const: dbi # DesignWare PCIe registers
> > +      - const: elbi # External local bus interface registers
> > +      - const: atu # ATU address space
> > +      - const: config # PCIe configuration space
> > +      - const: mhi # MHI registers
> > +
> > +  clocks:
> > +    minItems: 7
> > +    maxItems: 8
> > +
> > +  clock-names:
> > +    minItems: 7
> > +    items:
> > +      - const: aux # Auxiliary clock
> > +      - const: cfg # Configuration clock
> > +      - const: bus_master # Master AXI clock
> > +      - const: bus_slave # Slave AXI clock
> > +      - const: slave_q2a # Slave Q2A clock
> > +      - const: ddrss_sf_tbu # PCIe SF TBU clock
> > +      - const: noc_aggr # Aggre NoC PCIe AXI clock
> > +      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
> > +
> > +  resets:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  reset-names:
> > +    minItems: 1
> > +    items:
> > +      - const: pci # PCIe core reset
> > +      - const: link_down # PCIe link down reset
> > +
> > +oneOf:
> > +  - properties:
> > +      interrupts:
> > +        maxItems: 1
> > +      interrupt-names:
> > +        items:
> > +          - const: msi
> > +
> > +  - properties:
> > +      interrupts:
> > +        minItems: 8
> > +      interrupt-names:
> > +        items:
> > +          - const: msi0
> > +          - const: msi1
> > +          - const: msi2
> > +          - const: msi3
> > +          - const: msi4
> > +          - const: msi5
> > +          - const: msi6
> > +          - const: msi7
> 
> How does a given SoC have 1 or 8 interrupts? I guess it is possible. A 
> comment here would be helpful.
> 

No, this is due to kernel developers not able to find out the max MSI numbers
for each platforms out of the Qcom internal documentation.

Let it be for now, I will try to fetch these numbers to make it accurate later.

- Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 

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