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Wed, 17 Jan 2024 04:58:33 -0600 Received: from [172.24.227.9] (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40HAwTtZ073889; Wed, 17 Jan 2024 04:58:29 -0600 Message-ID: <92ceb1ea-78db-4bc4-af1f-a1690eaca24c@ti.com> Date: Wed, 17 Jan 2024 16:28:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , , , , , Subject: Re: [PATCH 2/3] dt-bindings: PCI: ti,j721e-pci-*: Add checks for max-link-speed Content-Language: en-US To: Krzysztof Kozlowski References: <20240117102526.557006-1-s-vadapalli@ti.com> <20240117102526.557006-3-s-vadapalli@ti.com> <4282b248-cb7f-4486-bde6-105a3aed6be2@linaro.org> From: Siddharth Vadapalli In-Reply-To: <4282b248-cb7f-4486-bde6-105a3aed6be2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 17/01/24 16:05, Krzysztof Kozlowski wrote: > On 17/01/2024 11:25, Siddharth Vadapalli wrote: >> Extend the existing compatible based checks for validating and enforcing >> the "max-link-speed" property. > > Based on what? Driver or hardware? Your entire change suggests you Hardware. The PCIe controller on AM64 SoC supports up to Gen2 link speed while the PCIe controllers on other SoCs support Gen3 link speed. > should just drop it from the binding, because this can be deduced from > compatible. Could you please clarify? Isn't the addition of the checks for "max-link-speed" identical to the checks which were added for "num-lanes", both of which are Hardware specific? -- Regards, Siddharth.