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bh=Ha7p2Qq9XUTjNwoHLIVXXPbHNGR1+vSuwUvn+P96Mv8=; b=IvUGtKqFmz3y2GYrhU6YiWEQTU/ZjOhWHVrVDZSK8/0T41iIM90wlKxcKmhLOLtlVK 5lVAMbj0ypiw0ijbxuWh1+dsSm6gzlq6U+VoqhxWKRz2Y952ELT0XpkCcHELgqFhPnhT cDCezIXr+s7ZvSYlna5nFLjkZ4FYaPebSfHt60pUVG5Ponz7U0sVR2vyQAZ0hE6OPfz0 rBSVCb2ZQfSjI5ImaGrEUZIPllSTf1M/zGSeHMxoTNK7G/E93u33HL9KStaoPCqyp24S Ha8jbC886q0/XeOK9SDgU6tcfLOaUvvEd6HQTsXi30KHEBUx29iNPd/4xvjitKxVa0x7 Hjsw== X-Gm-Message-State: AOJu0YwGrIpqoG993Z0e3gLOhDIz0mrti/GfT2aCtIqIzV4nU7mzDqUx Ts7kiCixCXAJ3c7fjbIiHKlB7+eePLXH9Q== X-Received: by 2002:a17:906:fe44:b0:a27:8fa0:b3ea with SMTP id wz4-20020a170906fe4400b00a278fa0b3eamr2894620ejb.3.1705508808392; Wed, 17 Jan 2024 08:26:48 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id tj14-20020a170907c24e00b00a2eb3d1aecdsm1205705ejc.65.2024.01.17.08.26.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jan 2024 08:26:47 -0800 (PST) Message-ID: <40d66ddc-8293-4213-a0bd-321262a1a3ef@linaro.org> Date: Wed, 17 Jan 2024 16:26:46 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 16/18] tty: serial: samsung: shrink the clock selection to 8 clocks Content-Language: en-US To: Sam Protsenko Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com References: <20240110102102.61587-1-tudor.ambarus@linaro.org> <20240110102102.61587-17-tudor.ambarus@linaro.org> From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 1/16/24 19:09, Sam Protsenko wrote: > On Wed, Jan 10, 2024 at 4:25 AM Tudor Ambarus wrote: >> >> provides a clock selection pool of maximum 4 clocks. > > Then maybe it makes sense to turn those two field into 4-bit bit > fields? More importantly, what particular problem does this patch > solve, is this optimization really needed, and why? I'm not saying > it's not needed, just that commit message might've been more verbose > about this. > I guess I could have been more verbose in the phrase from below and said that for arm64 ``struct s3c24xx_uart_info`` spans through 2 cachelines and contains 2 holes, and with a bit of love it can fit a single cacheline with no holes. The end goal is to reduce the memory footprint of that struct. I chose u8 and allowed a max of 8 clocks simple because it's large enough to allow more clocks than are supported by the driver now, and not too big to cause spanning of the structure through 2 cachelines. >> Update the driver to consider a pool selection of maximum 8 clocks. The >> final scope is to reduce the memory footprint of >> ``struct s3c24xx_uart_info``. >> >> Signed-off-by: Tudor Ambarus >> --- >> drivers/tty/serial/samsung_tty.c | 22 +++++++++++----------- >> 1 file changed, 11 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c >> index 436739cf9225..5df2bcebf9fb 100644 >> --- a/drivers/tty/serial/samsung_tty.c >> +++ b/drivers/tty/serial/samsung_tty.c >> @@ -81,11 +81,11 @@ struct s3c24xx_uart_info { >> unsigned long tx_fifomask; >> unsigned long tx_fifoshift; >> unsigned long tx_fifofull; >> - unsigned int def_clk_sel; >> - unsigned long num_clks; >> unsigned long clksel_mask; >> unsigned long clksel_shift; >> unsigned long ucon_mask; >> + u8 def_clk_sel; >> + u8 num_clks; >> u8 iotype; >>