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Thu, 18 Jan 2024 04:06:32 +0000 Received: from offworld (ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a270.dreamhost.com (Postfix) with ESMTPSA id 4TFq1g5QzGz71; Wed, 17 Jan 2024 20:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1705550792; bh=EJOE4oWc7zcPOVUmVEWhBrFQsdzfb6SMOjZRrmacEJ8=; h=Date:From:To:Cc:Subject:Content-Type; b=hjqGPt+tOJ8do4jmDlqsIQiQSztq48Lw89F5AcA72hJ7GPuJT1OAeNwzX7F+0mCmy Yym6VT7H5ovd7/gqxxEzRnwgxp+iSNXXfVAH3JUCQiNf/7UXmji4rBzkxEnHHoSg2Z LoF3F1waICIx+VzUJJSJnoli3rBH9yFEgvnHbCt8r2c38o0dtAfaoFX3P9P4M9Yhsa +fWT+7U6j/GQKFQvblDwwN+arKLgUmOtsMJiyDfOmy454DmIEP4s7M9w1phmo61cO9 r9UhwNQEurid62sjzlG8e0yLeQwHXeMxMQvBmVDxx6TN9csdGC0zs6sIHMWhuu2d/P 8pi2+YgdN+zsA== Date: Wed, 17 Jan 2024 20:06:25 -0800 From: Davidlohr Bueso To: Ira Weiny Cc: Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Dan Williams , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Larsen , Fan Ni Subject: Re: [PATCH v2] cxl/pci: Skip irq features if MSI/MSI-X are not supported Message-ID: References: <20240117-dont-fail-irq-v2-1-f33f26b0e365@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20240117-dont-fail-irq-v2-1-f33f26b0e365@intel.com> User-Agent: NeoMutt/20231221 On Wed, 17 Jan 2024, Ira Weiny wrote: >CXL 3.1 Section 3.1.1 states: > > "A Function on a CXL device must not generate INTx messages if > that Function participates in CXL.cache protocol or CXL.mem > protocols." > >The generic CXL memory driver only supports devices which use the >CXL.mem protocol. The current driver attempts to allocate MSI/MSI-X >vectors in anticipation of their need for mailbox interrupts or event >processing. However, the above requirement does not require a device to >support interrupts, only that they use MSI/MSI-X. For example, a device >may disable mailbox interrupts and either be configured for firmware >first or skip event processing and function. > >Dave Larsen reported that the following Intel / Agilex card does not >support interrupts on function 0. > > CXL: Intel Corporation Device 0ddb (rev 01) (prog-if 10 [CXL Memory Device (CXL 2.x)]) > >Rather than fail device probe if interrupts are not supported; flag that >irqs are not enabled and avoid features which require interrupts. >Emit messages appropriate for the situation to aid in debugging should >device behavior be unexpected due to a failure to allocate vectors. > >Note that it is possible for a device to have host based event >processing through polling. However, the driver does not support >polling and it is not anticipated to be generally required. Leave that >functionality to a future patch if such a device comes along. > >Reported-by: Dave Larsen >Reviewed-by: Dave Jiang >Reviewed-by: Fan Ni >Signed-off-by: Ira Weiny Yes, I suspected this might come up at some point. Reviewed-and-tested-by: Davidlohr Bueso