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Message-ID: <4762CA33.4080202@keyaccess.nl>
Date: Fri, 14 Dec 2007 19:23:47 +0100
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To: "H. Peter Anvin" <hpa@zytor.com>
CC: Ingo Molnar <mingo@elte.hu>, "David P. Reed" <dpreed@reed.com>,
       Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org,
       Ingo Molnar <mingo@redhat.com>, Pavel Machek <pavel@ucw.cz>
Subject: Re: [PATCH] x86_64: fix problems due to use of "outb" to port 80
 on some AMD64x2 laptops, etc.
References: <466F0941.9060201@reed.com> <1181682498.8176.224.camel@chaos> <469578CD.3080609@reed.com> <1184216528.12353.203.camel@chaos> <1184218962.12353.209.camel@chaos> <46964352.7040301@reed.com> <1184253339.12353.223.camel@chaos> <469697C6.50903@reed.com> <1184274754.12353.254.camel@chaos> <4761F193.7090400@reed.com> <20071214131502.GA14359@elte.hu> <4762C551.5070003@zytor.com>
In-Reply-To: <4762C551.5070003@zytor.com>
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From: Rene Herman <rene.herman@gmail.com>
Sender: linux-kernel-owner@vger.kernel.org
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On 14-12-07 19:02, H. Peter Anvin wrote:

> I believe this will suffer from the issue that was raised: this will use
> udelay() long before loop calibration (and no, we can't just "be 
> conservative" since there is no "conservative" value we can use.)
> 
> Worse, I suspect that at least the PIT, which may need to be used for 
> udelay calibration, is one of the devices that may be affected.  I have 
> seen the Verilog for a contemporary chipset, and it can only access the 
> PIT once per microsecond -- this actually has to do with the definition 
> of the PIT; some of the PIT operations are ill-defined if allowed at a 
> higher frequency than the PIT clock.

Was reported before indeed:

http://linux.derkeiler.com/Mailing-Lists/Kernel/2003-09/5764.html

Rene.

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