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From: Frank Wunderlich <frank-w@public-files.de>
To: Conor Dooley <conor@kernel.org>, AngeloGioacchino Del Regno
 <angelogioacchino.delregno@collabora.com>
Cc: Frank Wunderlich <linux@fw-web.de>, Michael Turquette
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 Sam Shih <sam.shih@mediatek.com>, Daniel Golle <daniel@makrotopia.org>,
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Subject: Aw: Re: [PATCH v3 1/2] dt-bindings: reset: mediatek: add MT7988
 reset IDs
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Date: Thu, 18 Jan 2024 23:00:00 +0100
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UI-OutboundReport: notjunk:1;M01:P0:Gzu+rTj6VvA=;AFUqbzs2KLld0OIuq1bzMhSKPgl
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 WR7gsIYRWrdXsS+lhb/FHdIOt+wwG8hBHQ6ihMBrnrUSgm8xTWHEJM+v6a4U3ZQYLeQPEUJn7
 omzxu8D1RDFlLgxRO9viMu0N/xh0Qr9W2niMCedv4y4VEjFJMhxK+ygXRKjwzastXE3TYNJea
 WlA+RXaGs7BDFDEXjBV1DJDzATdgGqXq8AnOW9CtWyrrirW9TJpTV0IRbj6No/L8d5pqf01oj
 E8+0bhGoBMcdz8f6cL6gqxMCoGGAH1tVzG9IlVljibVUcGPRy8IhPXyxK5yFok+EerEmSq2tL
 b5i84Et/qC1kETeXvhxKK7ew==
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> Gesendet: Donnerstag, 18. Januar 2024 um 17:49 Uhr
> Von: "Conor Dooley" <conor@kernel.org>
> On Wed, Jan 17, 2024 at 07:41:10PM +0100, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> >
> > Add reset constants for using as index in driver and dts.
> >
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> > v3:
> > - add pcie reset id as suggested by angelo
> >
> > v2:
> >  - add missing commit message and SoB
> >  - change value of infrareset to 0
> > ---
> >  include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/incl=
ude/dt-bindings/reset/mediatek,mt7988-resets.h
> > index 493301971367..0eb152889a89 100644
> > --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
> > +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
> > @@ -10,4 +10,10 @@
> >  /* ETHWARP resets */
> >  #define MT7988_ETHWARP_RST_SWITCH		0
> >
> > +/* INFRA resets */
> > +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST	0
> > +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST	1
>
> These are just "random" numbers, why not continue the numbering from the
> ETHWARP?

i can do...basicly these consts are used in DTS and driver only as index.

@angelo what do you think? I though also in leaving some space to allow gr=
ouping RST0 and RST1
when more consts are added, else the numbers are mixed up.

so e.g. let RST0 start at 20 and RST1 at 40 (or even higher, because RST0 =
and RST1 can have up to 32 resets).
That will allow adding more reset constants between my values and having r=
aising numbers.

regards Frank