Received-SPF: pass (google.com: domain of linux-kernel+bounces-31402-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
From: Frank Li <Frank.Li@nxp.com>
To: manivannan.sadhasivam@linaro.org
Cc: Frank.Li@nxp.com,
	bhelgaas@google.com,
	conor+dt@kernel.org,
	devicetree@vger.kernel.org,
	festevam@gmail.com,
	helgaas@kernel.org,
	hongxing.zhu@nxp.com,
	imx@lists.linux.dev,
	kernel@pengutronix.de,
	krzysztof.kozlowski+dt@linaro.org,
	krzysztof.kozlowski@linaro.org,
	kw@linux.com,
	l.stach@pengutronix.de,
	linux-arm-kernel@lists.infradead.org,
	linux-imx@nxp.com,
	linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org,
	lpieralisi@kernel.org,
	robh@kernel.org,
	s.hauer@pengutronix.de,
	shawnguo@kernel.org
Subject: [PATCH v9 07/16] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
Date: Fri, 19 Jan 2024 12:11:13 -0500
Message-Id: <20240119171122.3057511-8-Frank.Li@nxp.com>
In-Reply-To: <20240119171122.3057511-1-Frank.Li@nxp.com>
References: <20240119171122.3057511-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?VIEq/MpElqM6xiK1VC32ps7/3nAM52sQArtchuOHn/4XzgwMXRLuUByXV6es?=
 =?us-ascii?Q?cBZar/1ERcROoTpTexPFI7Xvqcg3ZoiIaXOSMTk23+p7NxyIpWqAE2z5HP22?=
 =?us-ascii?Q?htI8A1I49ZEX2b2qg3OE1bMtXbyvuaIKTE1hSlD6lSwFj6nvLl62k7h4c5cZ?=
 =?us-ascii?Q?RVCPC/8Np7smz/U62ez4uh7rU5OtTJTjAEArEloY0frqgwzaxG7wGctIXPpV?=
 =?us-ascii?Q?YcOOEOiJeJsLZazYdfG2ajJm1McTl0nIYymYPcybFe9qJQBicQ/9xF4QzOmi?=
 =?us-ascii?Q?6we813uorhKrecS8zLhtbfwknZHIxBJlfzwndMb4+wPn5WPttIQODsdCA/er?=
 =?us-ascii?Q?mvjklVAw8qAVN998A/MrAK2X9MCh0mPpmtbFD4KBMMZmVSAAi/IqoTzLLPyh?=
 =?us-ascii?Q?lFFnRZOESnj3YQktpK/vOIvK+OETjYyp2j3lXO4qTGTwP9ZhTvcECC+XDtDT?=
 =?us-ascii?Q?AxSg+fp0iMhcRF5UDw1t+kpnEZjR1piQsMqpLseliGPsHLmjSDjl7fdDacr8?=
 =?us-ascii?Q?etp0hIpBzkctSO8EisopAptLhy+0kkUWqZY8El2Ha5PKhMDGnwCVUuL5qYj7?=
 =?us-ascii?Q?O3rZmVjmdEvN/FYtVZs/l+0OPXNo7J8LuSorTU24P4nkA4eHNJwnTReRWXSa?=
 =?us-ascii?Q?FcEjt3LW+a0piFkt3iORAaHELzI9C/tzqdGGlBia4KegIU8e7EJS5h7Mb0rp?=
 =?us-ascii?Q?5e5PPBJq4JmPG2HOXFmXCEGC/J5qojuaBnSijq9jYOqP9KhaiaYQxS5MnQJC?=
 =?us-ascii?Q?kXxf6nBR0A3wwJdU2pVF2W0bfov+wLW/rF5LX5/gcu2xqdGA2C6iayszxwBe?=
 =?us-ascii?Q?ivn1f45pMw1Rym8ZxUSXvQnbjxn+RjHSOsDKcCAgagglRxpBDfv01aKvM4rY?=
 =?us-ascii?Q?mfAH5CCBOc0zQHuL2H2o4xKkg9vAsynfUUaBw0QNxaAJ1Xdj9o6t5Lzkrbss?=
 =?us-ascii?Q?7/wmmDxvHwMp/PUuTcMzWOEcMHdJ3DOWJmLfNY3RExGuEzw9w0AdVJIdsmkM?=
 =?us-ascii?Q?2/diAZZW87rUIkekLVy2PH2nPv60SV8fMP5oLIWV69AqL4gih27zLXEsU58l?=
 =?us-ascii?Q?LdxcRQW8ugmZzwooLDvLqmFekOTICQrb3o4LGmYz1xBvm9iN1hOffv8PqQy5?=
 =?us-ascii?Q?8ud6Us7gQHPGJQ8YkE6gPCBZEi+sZLb0wjznCKD5+Sche8wOCDG7RYoqmG3y?=
 =?us-ascii?Q?BgQigalMHCMMlBpYL+3uPOAry3Nh2IvfRMbOQjdp+/vP2Dv4cwPhGQw/S6RC?=
 =?us-ascii?Q?dSkVcxGWRZUwQYh4iptyiENw/fDQszY0ONx/HYp8rl/eZhtcWcRjcHL14jTw?=
 =?us-ascii?Q?f6iwW/F2TrGSWbhZNEh7UGUbwu/Kmb7cn4YJHadhgNnKsQrsu/BdU2LldmTA?=
 =?us-ascii?Q?Y4AobqH2q+1R6RtU+pHZl2X1z7dBnOaUjavXgcNPUnMWdJU9W54osRFAHauM?=
 =?us-ascii?Q?SbYapzASn/DhNsCYq6IY7+846eZCTKVywuKNLjety3aOCZTn03z54F4YuBrB?=
 =?us-ascii?Q?fusKsyqQaO+cpgjnYQ3vsOaD7gDrCOIqUquZan3eSgoGBQ/o+mAeDcIalPhl?=
 =?us-ascii?Q?gLBiUE/TlgrfcadKDQ0=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 4ff28796-fba8-4295-efa1-08dc1911cae8
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 17:12:19.0988
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: WPp5JriasvkZVsqLhdTDk67LeOGw/LMI42oRxOQ/KdolhQQK7snMXm573pdZ22HBy+5+O+4Ic6AQ7JOkmVRsLQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB9688

Add drvdata::mode_off and drvdata::mode_mask to simplify
imx6_pcie_configure_type() logic.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Chagne from v8 to v9
    - add Manivannan's review tag
    Change from v7 to v8
    - replace simple with simplify
    - remove reduntant comments about FILED_PREP
    Change from v3 to v7
    - none
    Change from v2 to v3
    - none
    Change from v1 to v2
    - use ffs() to fixe build error.
    
    Change from v2 to v3
    - none
    Change from v1 to v2
    - use ffs() to fixe build error.

 drivers/pci/controller/dwc/pci-imx6.c | 59 ++++++++++++++++++---------
 1 file changed, 39 insertions(+), 20 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index d19fcb54fde0d..8df07b71c93e5 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -68,6 +68,7 @@ enum imx6_pcie_variants {
 
 #define IMX6_PCIE_MAX_CLKS       6
 
+#define IMX6_PCIE_MAX_INSTANCES			2
 struct imx6_pcie_drvdata {
 	enum imx6_pcie_variants variant;
 	enum dw_pcie_device_mode mode;
@@ -78,6 +79,8 @@ struct imx6_pcie_drvdata {
 	const u32 clks_cnt;
 	const u32 ltssm_off;
 	const u32 ltssm_mask;
+	const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
+	const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
 };
 
 struct imx6_pcie {
@@ -174,32 +177,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 
 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 {
-	unsigned int mask, val, mode;
+	const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+	unsigned int mask, val, mode, id;
 
-	if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
+	if (drvdata->mode == DW_PCIE_EP_TYPE)
 		mode = PCI_EXP_TYPE_ENDPOINT;
 	else
 		mode = PCI_EXP_TYPE_ROOT_PORT;
 
-	switch (imx6_pcie->drvdata->variant) {
-	case IMX8MQ:
-	case IMX8MQ_EP:
-		if (imx6_pcie->controller_id == 1) {
-			mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
-			val  = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
-					  mode);
-		} else {
-			mask = IMX6Q_GPR12_DEVICE_TYPE;
-			val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
-		}
-		break;
-	default:
-		mask = IMX6Q_GPR12_DEVICE_TYPE;
-		val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
-		break;
-	}
+	id = imx6_pcie->controller_id;
+
+	/* If mode_mask[id] is zero, means each controller have its individual gpr */
+	if (!drvdata->mode_mask[id])
+		id = 0;
+
+	mask = drvdata->mode_mask[id];
+	val = mode << (ffs(mask) - 1);
 
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
 }
 
 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
@@ -1385,6 +1380,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clks_cnt = ARRAY_SIZE(imx6q_clks),
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX6SX] = {
 		.variant = IMX6SX,
@@ -1396,6 +1393,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clks_cnt = ARRAY_SIZE(imx6sx_clks),
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX6QP] = {
 		.variant = IMX6QP,
@@ -1408,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clks_cnt = ARRAY_SIZE(imx6q_clks),
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX7D] = {
 		.variant = IMX7D,
@@ -1417,6 +1418,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx7d-iomuxc-gpr",
 		.clk_names = imx6q_clks,
 		.clks_cnt = ARRAY_SIZE(imx6q_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MQ] = {
 		.variant = IMX8MQ,
@@ -1425,6 +1428,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mq-iomuxc-gpr",
 		.clk_names = imx8mq_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+		.mode_off[1] = IOMUXC_GPR12,
+		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 	},
 	[IMX8MM] = {
 		.variant = IMX8MM,
@@ -1434,6 +1441,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mm-iomuxc-gpr",
 		.clk_names = imx8mm_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MP] = {
 		.variant = IMX8MP,
@@ -1443,6 +1452,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mp-iomuxc-gpr",
 		.clk_names = imx8mm_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MQ_EP] = {
 		.variant = IMX8MQ_EP,
@@ -1452,6 +1463,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mq-iomuxc-gpr",
 		.clk_names = imx8mq_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+		.mode_off[1] = IOMUXC_GPR12,
+		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 	},
 	[IMX8MM_EP] = {
 		.variant = IMX8MM_EP,
@@ -1460,6 +1475,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mm-iomuxc-gpr",
 		.clk_names = imx8mm_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MP_EP] = {
 		.variant = IMX8MP_EP,
@@ -1468,6 +1485,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.gpr = "fsl,imx8mp-iomuxc-gpr",
 		.clk_names = imx8mm_clks,
 		.clks_cnt = ARRAY_SIZE(imx8mm_clks),
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 };
 
-- 
2.34.1