Received-SPF: pass (google.com: domain of linux-kernel+bounces-31408-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161;
From: Frank Li <Frank.Li@nxp.com>
To: manivannan.sadhasivam@linaro.org
Cc: Frank.Li@nxp.com,
	bhelgaas@google.com,
	conor+dt@kernel.org,
	devicetree@vger.kernel.org,
	festevam@gmail.com,
	helgaas@kernel.org,
	hongxing.zhu@nxp.com,
	imx@lists.linux.dev,
	kernel@pengutronix.de,
	krzysztof.kozlowski+dt@linaro.org,
	krzysztof.kozlowski@linaro.org,
	kw@linux.com,
	l.stach@pengutronix.de,
	linux-arm-kernel@lists.infradead.org,
	linux-imx@nxp.com,
	linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org,
	lpieralisi@kernel.org,
	robh@kernel.org,
	s.hauer@pengutronix.de,
	shawnguo@kernel.org
Subject: [PATCH v9 12/16] PCI: imx6: Add iMX95 PCIe Root Complex support
Date: Fri, 19 Jan 2024 12:11:18 -0500
Message-Id: <20240119171122.3057511-13-Frank.Li@nxp.com>
In-Reply-To: <20240119171122.3057511-1-Frank.Li@nxp.com>
References: <20240119171122.3057511-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?eNFSTFmMWlCA8K3yrHx8ZZbYtpuaOh65mxgfd98+MHXCwnk+sUdR1roq0h1e?=
 =?us-ascii?Q?5x9koIxQPuhcjb1EPsJ24XbegA3p8SIRvA9GqQ0g8QNd86qilGv+P6JVxly+?=
 =?us-ascii?Q?8Ktq9pCAkVCetTeMQDThh85ISK6VCY607V3fHVISout7KZZTTFwHkho2Gk0K?=
 =?us-ascii?Q?NYDyJ9jHnLl97YwURqH8OZGddviWVRMNylKiaRkw/Il2+MS3xEbR+vzh+7Lp?=
 =?us-ascii?Q?gRX3GThB/2a0pEnQHRl/nd+ekhbHiXC/crUGrBPsMRGn9lNHMLjMFOyzsnV1?=
 =?us-ascii?Q?cITftXkoUYL2qGtMG2d+lYmrz0sMIDo5kF5Kg/0/rmkfJ86VzNNJ479Kywq+?=
 =?us-ascii?Q?MT0lWUfcaych1D3EBgtZSDXd7WN/7d/itKnEVdvD27eroXUtQ/mUotcu6AWx?=
 =?us-ascii?Q?pOCUMkM7oGqbiiMK/TwDXc9ynWri+dRq3+ppMKbrUwufTA2xWY6F3sMvlVhV?=
 =?us-ascii?Q?obDvpm1w6q8qyTjBhaxplRFxv5BVI+zhXDsCuRbVmvC7+0hetsIH6JnBaurH?=
 =?us-ascii?Q?Tj3SNGjft2J+3xagPuMKBZelHKBIKYlaXrKxpCqdIOWyCIhlhTieT2ydabwD?=
 =?us-ascii?Q?hsiEDXHpnQFMdBYk/t8ArUt+vHziK38DNjr7ssfXB8KZJ8I1ohLIi/CR4gH/?=
 =?us-ascii?Q?+qbhHjv+RnrJ+RIK9UIjT0bQImgg3YXEoFHX26GDaBmPlortRiU3lIFS0Pap?=
 =?us-ascii?Q?WeTZwgu5snAm33iFLwOLmL96njs/Hejf6qH+yHa4GSMFY4c6OMSMGd3Jd7CN?=
 =?us-ascii?Q?2aM30vEWoHDUfrpJHLFas17g5oQrsa88a+cd4ypO54AQkP3UHxK4cEIJjpnF?=
 =?us-ascii?Q?Gi0/bcB1xoIwRNAYFyV44G6S1RuMwnElmoPDEdducxnWuCZ3YWcW0Lm8T660?=
 =?us-ascii?Q?oRg6ggFmJBpXmDcLnh1f9rDkBeAdPHARX6f8sBv1QApcIgZyfy77JGSzQ79g?=
 =?us-ascii?Q?gc6Do4Noa/IbOj4R3pPo/FHTPlB0zVglWPwR4wl4CBgk7zR+QZAeeaW9AhZa?=
 =?us-ascii?Q?bA3eEfAoDQr9h+Fan6/0BprTI8+drwGwBwrZ27IcaNwmV7b9ImwGgJ+WlUdP?=
 =?us-ascii?Q?ESV/I//pCC5JYkRjKbgsyOS6+JnUHsKyQ4kyIooYbICmQfACTW9RV6vB6CA5?=
 =?us-ascii?Q?jKcqQUs496VEKwbZmaDSySCv5epeRcLln4SaRCpWv1s6jTH3r/KA+c2eWJT1?=
 =?us-ascii?Q?I/iJYwm9Peah1mj72zqAggnBztKWT9n6XDaniKYWS4lxY2heQ4/n+lhckICO?=
 =?us-ascii?Q?oAMOloSJFHvfcRl4DU40XpyFGfmuUUJShCTKqPSPaIJX9ISCz//e5hBD2KnU?=
 =?us-ascii?Q?1X6hjklejg4pRBAgjJpn29SZBSnJ7GScLQsVniDPttPZznJpI06/AKY2XL2j?=
 =?us-ascii?Q?wZE1ledbqEXcT+5HW7yl5P5p0+4d8snMlcb4VOD1MeS6JsWSaj/ZjWo/LbWi?=
 =?us-ascii?Q?N7LuuXEetwPh8I6RKi11ZLzWn7ynMHXEGsagzNmv6+gaav8wWpKSfVpx2Vn1?=
 =?us-ascii?Q?RWDNy4h7nNNhnPQy0c9MiQa3O/zLNCyjI+LyZA8Tb1AgE+BdjoQ6LIhTo5hb?=
 =?us-ascii?Q?SapH1Mgg4UV7eCyVE9k=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 31df8c08-684b-4160-4c91-08dc1911da0b
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 17:12:44.4794
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: LATBRmNFEwXiX3Sbd5D2PyNfuJ9yuxzG0An5silopGiXg8Cqtsj6xqJrc5U7k2aE1ieijxDXQvJWyEenJP5Ntw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB9688

Add iMX95 PCIe Root Complex support.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Change from v8 to v9
    - Add mani's review tag
    
    Change from v7 to v8
    - Update commit subject
    - add const from regmap
    - remove unnessary logic in imx6_pcie_deassert_core_reset()
    
    Change from v4 to v7
    - none
    Change from v1 to v3
    - none

 drivers/pci/controller/dwc/pci-imx6.c | 82 +++++++++++++++++++++++++--
 1 file changed, 77 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index dad192f38e702..1cfa5f14f18f3 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -42,6 +42,25 @@
 #define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
 
+#define IMX95_PCIE_PHY_GEN_CTRL			0x0
+#define IMX95_PCIE_REF_USE_PAD			BIT(17)
+
+#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
+#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
+
+#define IMX95_PCIE_SS_RW_REG_0			0xf0
+#define IMX95_PCIE_REF_CLKEN			BIT(23)
+#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
+
+#define IMX95_PE0_GEN_CTRL_1			0x1050
+#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
+
+#define IMX95_PE0_GEN_CTRL_3			0x1058
+#define IMX95_PCIE_LTSSM_EN			BIT(0)
+
+#define IMX95_PE0_PM_STS			0x1064
+#define IMX95_PCIE_PM_LINKST_IN_L2		BIT(14)
+
 #define to_imx6_pcie(x)	dev_get_drvdata((x)->dev)
 
 enum imx6_pcie_variants {
@@ -52,6 +71,7 @@ enum imx6_pcie_variants {
 	IMX8MQ,
 	IMX8MM,
 	IMX8MP,
+	IMX95,
 	IMX8MQ_EP,
 	IMX8MM_EP,
 	IMX8MP_EP,
@@ -63,6 +83,7 @@ enum imx6_pcie_variants {
 #define IMX6_PCIE_FLAG_HAS_PHYDRV			BIT(3)
 #define IMX6_PCIE_FLAG_HAS_APP_RESET		BIT(4)
 #define IMX6_PCIE_FLAG_HAS_PHY_RESET		BIT(5)
+#define IMX6_PCIE_FLAG_HAS_SERDES		BIT(6)
 
 #define imx6_check_flag(pci, val)     (pci->drvdata->flags & val)
 
@@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
+static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+{
+	regmap_update_bits(imx6_pcie->iomuxc_gpr,
+			IMX95_PCIE_SS_RW_REG_0,
+			IMX95_PCIE_PHY_CR_PARA_SEL,
+			IMX95_PCIE_PHY_CR_PARA_SEL);
+
+	regmap_update_bits(imx6_pcie->iomuxc_gpr,
+			   IMX95_PCIE_PHY_GEN_CTRL,
+			   IMX95_PCIE_REF_USE_PAD, 0);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr,
+			   IMX95_PCIE_SS_RW_REG_0,
+			   IMX95_PCIE_REF_CLKEN,
+			   IMX95_PCIE_REF_CLKEN);
+
+	return 0;
+}
+
 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 {
 	const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
@@ -575,6 +614,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 				   IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 		break;
 	case IMX7D:
+	case IMX95:
 		break;
 	case IMX8MM:
 	case IMX8MM_EP:
@@ -1280,12 +1320,32 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->turnoff_reset);
 	}
 
+	if (imx6_pcie->drvdata->gpr) {
 	/* Grab GPR config register range */
-	imx6_pcie->iomuxc_gpr =
-		 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
-	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
-		dev_err(dev, "unable to find iomuxc registers\n");
-		return PTR_ERR(imx6_pcie->iomuxc_gpr);
+		imx6_pcie->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
+		if (IS_ERR(imx6_pcie->iomuxc_gpr))
+			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+					     "unable to find iomuxc registers\n");
+	}
+
+	if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
+		void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
+
+		if (IS_ERR(off))
+			return dev_err_probe(dev, PTR_ERR(off),
+					     "unable to find serdes registers\n");
+
+		static const struct regmap_config regmap_config = {
+			.reg_bits = 32,
+			.val_bits = 32,
+			.reg_stride = 4,
+		};
+
+		imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config);
+		if (IS_ERR(imx6_pcie->iomuxc_gpr))
+			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+					     "unable to find iomuxc registers\n");
 	}
 
 	/* Grab PCIe PHY Tx Settings */
@@ -1458,6 +1518,17 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.mode_off[0] = IOMUXC_GPR12,
 		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
+	[IMX95] = {
+		.variant = IMX95,
+		.flags = IMX6_PCIE_FLAG_HAS_SERDES,
+		.clk_names = imx8mq_clks,
+		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
+		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
+		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
+		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
+		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+		.init_phy = imx95_pcie_init_phy,
+	},
 	[IMX8MQ_EP] = {
 		.variant = IMX8MQ_EP,
 		.flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
@@ -1502,6 +1573,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
 	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
 	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
+	{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
 	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
 	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
 	{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
-- 
2.34.1