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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Jan 19, 2024 at 12:36=E2=80=AFPM Radhey Shyam Pandey wrote: > > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey > --- [snip] > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-mode= pin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.= yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yam= l > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yam= l > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta > + - Mubin Sayyed > + - Radhey Shyam Pandey > > properties: > compatible: For GPIO: Acked-by: Bartosz Golaszewski [snip]