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Sat, 20 Jan 2024 11:59:46 -0800 Date: Sat, 20 Jan 2024 11:59:45 -0800 From: Nicolin Chen To: "will@kernel.org" , Robin Murphy CC: Jason Gunthorpe , "joro@8bytes.org" , "jean-philippe@linaro.org" , Alistair Popple , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Add nents_per_pgtable in struct io_pgtable_cfg Message-ID: References: <0fe68babdb3a07adf024ed471fead4e3eb7e703f.1692693557.git.nicolinc@nvidia.com> <61f9b371-7c45-26b1-ec0f-600765280c89@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D4:EE_|DM4PR12MB7718:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c1c5f57-34ef-4ffe-f994-08dc19f2628b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2024 20:00:00.4325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c1c5f57-34ef-4ffe-f994-08dc19f2628b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7718 Hi Robin/Will, On Tue, Aug 29, 2023 at 02:25:10PM -0700, Robin Murphy wrote: > > Also, what we need is actually an arbitrary number for max_tlbi_ops. > > And I think it could be irrelevant to the page size, i.e. either a > > 4K pgsize or a 64K pgsize could use the same max_tlbi_ops number, > > because what eventually impacts the latency is the number of loops > > of building/issuing commands. > > Although there is perhaps a counter-argument for selective invalidation, > that if you're using 64K pages to improve TLB hit rates vs. 4K, then you > have more to lose from overinvalidation, so maybe a single threshold > isn't so appropriate for both. > > Yes, ultimately it all comes down to picking an arbitrary number, but > the challenge is that we want to pick a *good* one, and ideally have > some reasoning behind it. As Will suggested, copying what the mm layer > does gives us an easy line of reasoning, even if it's just in the form > of passing the buck. And that's actually quite attractive, since > otherwise we'd then have to get into the question of what really is the > latency of building and issuing commands, since that clearly depends on > how fast the CPU is, and how fast the SMMU is, and how busy the SMMU is, > and how large the command queue is, and how many other CPUs are also > contending for the command queue... and very quickly it becomes hard to > believe that any simple constant can be good for all possible systems. So, here we have another request to optimize this number further, though the merged arbitrary number copied from MMU side could fix the soft lockup. The iommu_unmap delay with a 500MB buffer is not quite satisfying on our testing chip, since the threshold now for max_tlbi_ops is at 512MB for 64K pgsize (8192 * 64KB). As Robin remarked, this could be really a case-by-case situation. So, I wonder if we can rethink of adding a configurable threshold that has a default value at its current setup matching MMU side. If this is acceptable, what can be the preferable way of having a configuration: a per-SMMU or a per-IOMMU-group sysfs node? I am open for any other option too. Also, this would be added to the arm_smmu_inv_range_too_big() in Jason's patch here: https://lore.kernel.org/linux-iommu/20240115153152.GA50608@ziepe.ca/ Thanks Nicolin