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Message-ID: <9a5711b6-5e8e-4fcb-bea6-d5f9893762eb@phytec.de>
Date: Mon, 22 Jan 2024 03:54:24 +0100
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Subject: Re: [PATCH] arm64: dts: ti: Disable clock output of the ethernet PHY
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To: Nathan Morrisson <nmorrisson@phytec.com>, <nm@ti.com>, <vigneshr@ti.com>,
	<kristo@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>
CC: <devicetree@vger.kernel.org>, <upstream@lists.phytec.de>,
	<linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
References: <20240119225257.403222-1-nmorrisson@phytec.com>
From: Wadim Egorov <w.egorov@phytec.de>
In-Reply-To: <20240119225257.403222-1-nmorrisson@phytec.com>
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Am 19.01.24 um 23:52 schrieb Nathan Morrisson:
> The clock on the ethernet1 PHY is turned on by default. This turns
> the clock off as we do not use it.
>
> Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>

Reviewed-by: Wadim Egorov <w.egorov@phytec.de>


> ---
>   arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts
> index 4bc0134c987d..3173f6eca7ca 100644
> --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts
> @@ -222,6 +222,7 @@ &cpsw3g_mdio {
>   	cpsw3g_phy3: ethernet-phy@3 {
>   		compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
>   		reg = <3>;
> +		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
>   		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>   		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>   	};