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From: "Mehta, Piyush" <piyush.mehta@amd.com>
To: "Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>, "dlemoal@kernel.org"
	<dlemoal@kernel.org>, "cassel@kernel.org" <cassel@kernel.org>,
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	<mubin.sayyed@amd.com>, "Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>
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	<linux-usb@vger.kernel.org>, "git (AMD-Xilinx)" <git@amd.com>
Subject: RE: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
Thread-Topic: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
Thread-Index: AQHaSsvSSnpmMxSc+EyR1P4Gwr3GubDlR8IA
Date: Mon, 22 Jan 2024 04:54:12 +0000
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> -----Original Message-----
> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> Sent: Friday, January 19, 2024 5:06 PM
> To: dlemoal@kernel.org; cassel@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> linus.walleij@linaro.org; brgl@bgdev.pl; Simek, Michal
> <michal.simek@amd.com>; p.zabel@pengutronix.de;
> gregkh@linuxfoundation.org; Mehta, Piyush <piyush.mehta@amd.com>;
> Sayyed, Mubin <mubin.sayyed@amd.com>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>
> Cc: linux-ide@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-usb@vger.kernel.org; git (AMD-Xilinx)
> <git@amd.com>
> Subject: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
>=20
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xili=
nx
> udc controller maintainership duties to Mubin and Radhey.
>=20
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

Acked-by: Piyush Mehta <piyush.mehta@amd.com>

> ---
>  Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml      | 3 ++-
>  .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml     | 3 ++-
>  Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
>  Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml         | 3 ++-
>  Documentation/devicetree/bindings/usb/microchip,usb5744.yaml   | 3 ++-
>  Documentation/devicetree/bindings/usb/xlnx,usb2.yaml           | 3 ++-
>  6 files changed, 12 insertions(+), 6 deletions(-)
>=20
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Ceva AHCI SATA Controller
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  description: |
>    The Ceva SATA controller mostly conforms to the AHCI interface with so=
me
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.ya
> +++ ml
> @@ -12,7 +12,8 @@ description:
>    PS_MODE). Every pin can be configured as input/output.
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  properties:
>    compatible:
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.ya=
ml
> b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> index 49db66801429..1f1b42dde94d 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Zynq UltraScale+ MPSoC and Versal reset
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  description: |
>    The Zynq UltraScale+ MPSoC and Versal has several different resets.
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index bb373eb025a5..00f87a558c7d 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Xilinx SuperSpeed DWC3 USB SoC controller
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  properties:
>    compatible:
> diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> index 6d4cfd943f58..445183d9d6db 100644
> --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> @@ -16,8 +16,9 @@ description:
>    USB 2.0 traffic.
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
>    - Michal Simek <michal.simek@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  properties:
>    compatible:
> diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> index 868dffe314bc..a7f75fe36665 100644
> --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Xilinx udc controller
>=20
>  maintainers:
> -  - Piyush Mehta <piyush.mehta@amd.com>
> +  - Mubin Sayyed <mubin.sayyed@amd.com>
> +  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>=20
>  properties:
>    compatible:
> --
> 2.34.1