Received: by 2002:a05:7412:7c14:b0:fa:6e18:a558 with SMTP id ii20csp197699rdb; Mon, 22 Jan 2024 00:47:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHMSX0YU2xrUOFr5GlF1CZZkf5cuYHvyQ/k8G+xUGWg+lnkXxPmQQ/K5B4VqtjMKeVPxs4U X-Received: by 2002:a05:622a:10a:b0:42a:3cb9:2a81 with SMTP id u10-20020a05622a010a00b0042a3cb92a81mr2394438qtw.14.1705913224540; Mon, 22 Jan 2024 00:47:04 -0800 (PST) Return-Path: Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id g9-20020ac85d49000000b00429fe106886si5168353qtx.500.2024.01.22.00.47.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 00:47:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-32547-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="U/v3RbBT"; arc=fail (signature failed); spf=pass (google.com: domain of linux-kernel+bounces-32547-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-32547-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 42B761C226A5 for ; Mon, 22 Jan 2024 08:47:04 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6D27539AD7; Mon, 22 Jan 2024 08:46:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="U/v3RbBT" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2065.outbound.protection.outlook.com [40.107.100.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D11839846; Mon, 22 Jan 2024 08:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.65 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913175; cv=fail; b=uwBMWdSYLdL0HO7Lxs7bFbyQXijww6eVnOmb31Ucr7yYiIOmOz8l2LcurGtw4WxMYHQAuuk8i72Uv8l8rHzSVyVnYGo4n9yP+mnebKBLEPm90CiK0W+DHztVOiLFbxJqhVA7gpUnJkxIFVOPWmSNbCuuu6FuvOyc2ISaOsfW97g= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913175; c=relaxed/simple; bh=2lvEeibgpcsPhkDGLuPvCbJk7df3PcEFc/h04Qs3RSo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sOYecpvXfjBmZGoJyxH9IbqUZVSy4OfH3QjXbPNPD0QuOMV2JbalT6+uoWoPJd9TP9xe2xCbOPqUKcbtrj+5bxS6E5fgWKAW9wa2QLCk5glgql41RCP/B16pmOMs9+EwjN+E883D43Am+LdPnystwVsXDcNCV3Va3td7DfUioqI= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=U/v3RbBT; arc=fail smtp.client-ip=40.107.100.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=L3ixyE27np2GhRznJB18hAxNBF8wkdpum6OBSti4emluMTZJZKJKk1aXxqu/dalWDGeLX1j69Vkf9co70tHHzh799/G9fv4+kGrB5AJjx4JN7+9/aR1c8j1ruEhSCsF2XkOsT4Ofxfpe9L1FaDO2O/6AKmMjLID9xWib5CgF9kcm+Qwmwy2mbm9davxjpFfFHtc4rHSDqgsmtcAbVRi33ydGYEPj38J547Gg8odF8pa4G/ZaEilnkH9+chbMBsT2uD+PjdYPcnGtpoUm/1fGX95Ggsvw74fjaXZgmF4iGlL2fpBzJQaPVGRQX8YYMPwQfSMczCKoRiw81IQtZ+0t0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DcvfQSSnH+4J0JigX21NM6c5EIhSO2RCi7FuBNCnepo=; b=RkAA5qFvfhtc9/9g0ZipexIP29butHHkvPEElWdlbsUeZpEvoKrq20YidnKBhFCDnIaHXn/prJ93boZYMvpC+9ZQ/AFO62QNiogxKDXZwVdAwoDkbko4LCAu6Sp2lzZvcz8Whcmum4QCIXPCwjbzhNCsu7PFhFIxr5cNq6godKcjd1CwdIjwh+4/m1mGRC6crqSj343jNzIX03XF+vpbNkL3T3Ak8RoCzCHS57yIMkynWLlYrq/44l1nGM97vyT563WAYbRx0q+gBH/rbEhwkF8fm78uhjbIfku4PIToWN/+iEzJDd3wifNizmaJCeg5lI3CMPrYZA5ZLfKcLGYyhg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DcvfQSSnH+4J0JigX21NM6c5EIhSO2RCi7FuBNCnepo=; b=U/v3RbBTuqXIbiH6uQMFKxriMFAstN66ApcZfyG6elW+ggTyKDuIjr0BjRUdGBwzNXcJA6Khr4sDYER9+q+pYtHzCZkU5E6ct6xxkVLrIAE/5o27ug8U2I6RVWR7vmC+UFmfnmwM3RiWSa4jH8mN+T8R5AuRSInE+IRF6XPVxsocsWefmmaWe6EM6XHxyOqAeTxERHQ/riIto0IvPEbedhVKOQcY2kHEQH5D4mZTAEffAwKmno+mc7q5LQz9nC7XopTEonE1Q2VMspb6PqlX5FSigH3DJOgdw4VB945HHi/SNY8llmFViDJpP/hfnmRR9FgB22cvjBYkJGkbclK+8w== Received: from SJ0PR03CA0012.namprd03.prod.outlook.com (2603:10b6:a03:33a::17) by IA0PR12MB8929.namprd12.prod.outlook.com (2603:10b6:208:484::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.32; Mon, 22 Jan 2024 08:46:10 +0000 Received: from SJ5PEPF000001CD.namprd05.prod.outlook.com (2603:10b6:a03:33a:cafe::f0) by SJ0PR03CA0012.outlook.office365.com (2603:10b6:a03:33a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.34 via Frontend Transport; Mon, 22 Jan 2024 08:46:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ5PEPF000001CD.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.16 via Frontend Transport; Mon, 22 Jan 2024 08:46:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 22 Jan 2024 00:46:00 -0800 Received: from dev-r-vrt-155.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 22 Jan 2024 00:45:55 -0800 From: Danielle Ratson To: CC: , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH net-next 2/9] mlxsw: Implement ethtool operation to write to a transceiver module EEPROM Date: Mon, 22 Jan 2024 10:45:23 +0200 Message-ID: <20240122084530.32451-3-danieller@nvidia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122084530.32451-1-danieller@nvidia.com> References: <20240122084530.32451-1-danieller@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|IA0PR12MB8929:EE_ X-MS-Office365-Filtering-Correlation-Id: d71a7a9b-7e2b-4657-bfef-08dc1b26951f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Gs6JeXDb+D1Wkc99a0s/6Nh/+Ajf5NHn6y2gbvvOHzj3OvC+AWY5IzGCsSxR2vkMwlNYYOwiruNTFfGU4cAmemle3tPucVGBiEXavnp4RhgzBjm5TNBnUxJjyAFP8UJYPDkHEEKYqzBiGf+vNJJGrjD4F69pNOmBV+yYdBwZRg4LRsYsblnrDSYcWOorix1yVzODTd/mHh2AOuiRVyeWWvvK4e/LFaoFGe3JNLbrPK2WezohzxET3ADt6QNhM0gG98DCVSf/eeBWVY2bdlJPMBoh09DiCB7w3zdtwJUhiqgjxz7PhZ7I5eP886V/kBMuAhoBmyi9sAHulOweVdUrvaMsYgNPNdhmJRxD47dH/RdTxY+gB61sIAtlFEFnTHjPODWgkOJleQq5CjSoD5vkzhEOzoE5UnyqZIjh6Bt7gqsxVu+gm8wmCShAcQw7/aAQiIzev/C1X72OESJOJSvICFEltacwNBgO1xaRgLQ6A9xslaKsWx+iKLSpe1hgANzJjg1FVLw1JNOqMEwfg8DbS3SLMNdQ0JoOMdpTAjXd2SjfJb97FMvrmtGp707YXaUNTlKJXBHUmxXBlYwWBZm3wPYEbc2DphifxBWD8B+RDvyXOm31DfLQjmUnbsI4ulzeyPZBcQCPEJ2Go1xjkJNXiEpDy+CcA5THJtJGHyvlwjc2haHsRG9ZOmmBfrrnGslyLESte2qbUT6GwwKLXJY0lX0bh9swId23M7OeBMpCxn8= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(136003)(396003)(346002)(230922051799003)(1800799012)(82310400011)(451199024)(64100799003)(186009)(46966006)(40470700004)(36840700001)(356005)(7636003)(82740400003)(36756003)(40460700003)(40480700001)(86362001)(83380400001)(426003)(16526019)(336012)(26005)(107886003)(1076003)(2616005)(36860700001)(316002)(70586007)(70206006)(8936002)(8676002)(6666004)(54906003)(478600001)(6916009)(47076005)(2906002)(5660300002)(41300700001)(4326008)(7416002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2024 08:46:10.3892 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d71a7a9b-7e2b-4657-bfef-08dc1b26951f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8929 From: Ido Schimmel Implement the ethtool_ops::set_module_eeprom_by_page operation to allow ethtool to write to a transceiver module EEPROM, in a similar fashion to the ethtool_ops::get_module_eeprom_by_page operation. Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata --- .../net/ethernet/mellanox/mlxsw/core_env.c | 57 +++++++++++++++++++ .../net/ethernet/mellanox/mlxsw/core_env.h | 6 ++ drivers/net/ethernet/mellanox/mlxsw/minimal.c | 15 +++++ .../mellanox/mlxsw/spectrum_ethtool.c | 15 +++++ 4 files changed, 93 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c index 53b150b7ae4e..79e4c745ac3b 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c @@ -513,6 +513,63 @@ mlxsw_env_get_module_eeprom_by_page(struct mlxsw_core *mlxsw_core, } EXPORT_SYMBOL(mlxsw_env_get_module_eeprom_by_page); +int +mlxsw_env_set_module_eeprom_by_page(struct mlxsw_core *mlxsw_core, + u8 slot_index, u8 module, + const struct ethtool_module_eeprom *page, + struct netlink_ext_ack *extack) +{ + struct mlxsw_env *mlxsw_env = mlxsw_core_env(mlxsw_core); + u32 bytes_written = 0; + u16 device_addr; + int err; + + if (!mlxsw_env_linecard_is_active(mlxsw_env, slot_index)) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot write to EEPROM of a module on an inactive line card"); + return -EIO; + } + + err = mlxsw_env_validate_module_type(mlxsw_core, slot_index, module); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "EEPROM is not equipped on port module type"); + return err; + } + + device_addr = page->offset; + + while (bytes_written < page->length) { + char mcia_pl[MLXSW_REG_MCIA_LEN]; + char eeprom_tmp[128] = {}; + u8 size; + + size = min_t(u8, page->length - bytes_written, + mlxsw_env->max_eeprom_len); + + mlxsw_reg_mcia_pack(mcia_pl, slot_index, module, page->page, + device_addr + bytes_written, size, + page->i2c_address); + mlxsw_reg_mcia_bank_number_set(mcia_pl, page->bank); + memcpy(eeprom_tmp, page->data + bytes_written, size); + mlxsw_reg_mcia_eeprom_memcpy_to(mcia_pl, eeprom_tmp); + + err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcia), mcia_pl); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to access module's EEPROM"); + return err; + } + + err = mlxsw_env_mcia_status_process(mcia_pl, extack); + if (err) + return err; + + bytes_written += size; + } + + return 0; +} +EXPORT_SYMBOL(mlxsw_env_set_module_eeprom_by_page); + static int mlxsw_env_module_reset(struct mlxsw_core *mlxsw_core, u8 slot_index, u8 module) { diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.h b/drivers/net/ethernet/mellanox/mlxsw/core_env.h index a197e3ae069c..e4ff17869400 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_env.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.h @@ -28,6 +28,12 @@ mlxsw_env_get_module_eeprom_by_page(struct mlxsw_core *mlxsw_core, const struct ethtool_module_eeprom *page, struct netlink_ext_ack *extack); +int +mlxsw_env_set_module_eeprom_by_page(struct mlxsw_core *mlxsw_core, + u8 slot_index, u8 module, + const struct ethtool_module_eeprom *page, + struct netlink_ext_ack *extack); + int mlxsw_env_reset_module(struct net_device *netdev, struct mlxsw_core *mlxsw_core, u8 slot_index, u8 module, u32 *flags); diff --git a/drivers/net/ethernet/mellanox/mlxsw/minimal.c b/drivers/net/ethernet/mellanox/mlxsw/minimal.c index 6b98c3287b49..e52be38b5495 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/minimal.c +++ b/drivers/net/ethernet/mellanox/mlxsw/minimal.c @@ -140,6 +140,20 @@ mlxsw_m_get_module_eeprom_by_page(struct net_device *netdev, page, extack); } +static int +mlxsw_m_set_module_eeprom_by_page(struct net_device *netdev, + const struct ethtool_module_eeprom *page, + struct netlink_ext_ack *extack) +{ + struct mlxsw_m_port *mlxsw_m_port = netdev_priv(netdev); + struct mlxsw_core *core = mlxsw_m_port->mlxsw_m->core; + + return mlxsw_env_set_module_eeprom_by_page(core, + mlxsw_m_port->slot_index, + mlxsw_m_port->module, + page, extack); +} + static int mlxsw_m_reset(struct net_device *netdev, u32 *flags) { struct mlxsw_m_port *mlxsw_m_port = netdev_priv(netdev); @@ -181,6 +195,7 @@ static const struct ethtool_ops mlxsw_m_port_ethtool_ops = { .get_module_info = mlxsw_m_get_module_info, .get_module_eeprom = mlxsw_m_get_module_eeprom, .get_module_eeprom_by_page = mlxsw_m_get_module_eeprom_by_page, + .set_module_eeprom_by_page = mlxsw_m_set_module_eeprom_by_page, .reset = mlxsw_m_reset, .get_module_power_mode = mlxsw_m_get_module_power_mode, .set_module_power_mode = mlxsw_m_set_module_power_mode, diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c index 0f29e9c19411..d4fd7f7d660f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c @@ -1067,6 +1067,20 @@ mlxsw_sp_get_module_eeprom_by_page(struct net_device *dev, module, page, extack); } +static int +mlxsw_sp_set_module_eeprom_by_page(struct net_device *dev, + const struct ethtool_module_eeprom *page, + struct netlink_ext_ack *extack) +{ + struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); + struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; + u8 slot_index = mlxsw_sp_port->mapping.slot_index; + u8 module = mlxsw_sp_port->mapping.module; + + return mlxsw_env_set_module_eeprom_by_page(mlxsw_sp->core, slot_index, + module, page, extack); +} + static int mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info) { @@ -1256,6 +1270,7 @@ const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { .get_module_info = mlxsw_sp_get_module_info, .get_module_eeprom = mlxsw_sp_get_module_eeprom, .get_module_eeprom_by_page = mlxsw_sp_get_module_eeprom_by_page, + .set_module_eeprom_by_page = mlxsw_sp_set_module_eeprom_by_page, .get_ts_info = mlxsw_sp_get_ts_info, .get_eth_phy_stats = mlxsw_sp_get_eth_phy_stats, .get_eth_mac_stats = mlxsw_sp_get_eth_mac_stats, -- 2.40.1