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Mon, 22 Jan 2024 04:01:17 -0600 Received: from [172.24.227.9] (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40MA1C0r016811; Mon, 22 Jan 2024 04:01:12 -0600 Message-ID: Date: Mon, 22 Jan 2024 15:31:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , , , , , Subject: Re: [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC Content-Language: en-US To: Conor Dooley References: <20240122064457.664542-1-s-vadapalli@ti.com> <20240122-getting-drippy-bb22a0634092@spud> From: Siddharth Vadapalli In-Reply-To: <20240122-getting-drippy-bb22a0634092@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hello Conor, On 22/01/24 15:17, Conor Dooley wrote: > On Mon, Jan 22, 2024 at 12:14:57PM +0530, Siddharth Vadapalli wrote: >> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller. >> The controller on J722S SoC is similar to the one present on TI's AM64 >> SoC, with the difference being that the controller on AM64 SoC supports >> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed. >> >> Update the bindings with a new compatible for J722S SoC. > > Since the difference is just that this device supports a higher link > speed, should it not have a fallback compatible to the am64 variant? > Or is the programming model different for this device for the lower link > speeds different? Thank you for reviewing the patch. I shall add the same fallback compatible that am64 has which is "ti,j721e-pcie-host". I will post the v3 patch with this change if that's acceptable. -- Regards, Siddharth.