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Message-ID: <069e3e67-fd93-4af4-905e-d4087a5b3153@kernel.org>
Date: Mon, 22 Jan 2024 19:28:53 +0900
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Subject: Re: [PATCH 1/2] ata: ahci_ceva: fix error handling for Xilinx GT PHY
 support
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To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>, cassel@kernel.org,
 richardcochran@gmail.com, piyush.mehta@xilinx.com, axboe@kernel.dk,
 michal.simek@amd.com
Cc: linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org, git@amd.com,
 Piyush Mehta <piyush.mehta@amd.com>
References: <1705604904-471889-1-git-send-email-radhey.shyam.pandey@amd.com>
 <1705604904-471889-2-git-send-email-radhey.shyam.pandey@amd.com>
From: Damien Le Moal <dlemoal@kernel.org>
Organization: Western Digital Research
In-Reply-To: <1705604904-471889-2-git-send-email-radhey.shyam.pandey@amd.com>
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On 1/19/24 04:08, Radhey Shyam Pandey wrote:
> From: Piyush Mehta <piyush.mehta@amd.com>
> 
> Platform clock and phy error resources are not cleaned up in Xilinx GT PHY
> error path. To fix introduce error label for ahci_platform_disable_clks and
> phy_power_off/exit and call them in error path. No functional change.
> 
> Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy")
> Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> ---

Your patch format is strange... There is one too many "---" line here.

Other than that, looks OK to me.

Reviewed-by: Damien Le Moal <dlemoal@kernel.org>


-- 
Damien Le Moal
Western Digital Research