Date: Sat, 15 Dec 2007 12:06:15 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: Chuck Ebbert <cebbert@redhat.com>
cc: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>,
       linux-kernel@vger.kernel.org
Subject: Re: x86_64 and AMD with C1E
In-Reply-To: <471FBC09.8050201@redhat.com>
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On Wed, 24 Oct 2007, Chuck Ebbert wrote:

> On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
> >>>
> >>> I fill something wrong here.
> >>> Is it possible to reduce the amount of timer interrupts?
> >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
> >>>
> >> How are you disabling C1E?
> >>
> >>
> > dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic
> > initialization code. I make it for test purpose only, so i do not produce a
> > patch.
> > 
> 
> Why does disabling C1E disable C1, C2 and C3?
> 
> Thomas, in the case of the machines where C1E is disabled on CPU 0 but
> enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the
> vendor just forgot to disable CPU 1...

This whole C1E business is a lot of magic trickery in the guts of the
BIOS. I have an X2 box here with an extrem interesting behaviour. C1E
is not advertised at all, but the box freezes with the same symptoms
unless I disable the local apic timer on the kernel command line. I
have no clue how this works internally.

     tglx
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