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Tue, 23 Jan 2024 10:52:41 +0100 Received: from mfe by ptx.whiteo.stw.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1rSDST-001LYv-5H; Tue, 23 Jan 2024 10:52:41 +0100 Date: Tue, 23 Jan 2024 10:52:41 +0100 From: Marco Felsch To: "Peng Fan (OSS)" Cc: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, Peng Fan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] clocksource: timer-imx-sysctr: support i.MX95 Message-ID: <20240123095241.66nrgkkrdth6g32w@pengutronix.de> References: <20240122092225.2083191-1-peng.fan@oss.nxp.com> <20240122092225.2083191-2-peng.fan@oss.nxp.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240122092225.2083191-2-peng.fan@oss.nxp.com> User-Agent: NeoMutt/20180716 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Hi Peng, On 24-01-22, Peng Fan (OSS) wrote: > From: Peng Fan > > To i.MX95 System counter module, we use Read register space to get > the counter, not the Control register space to get the counter, because > System Manager firmware not allow Linux to read Control register space. > > Signed-off-by: Peng Fan > --- > drivers/clocksource/timer-imx-sysctr.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c > index 5a7a951c4efc..3d3bc16388ed 100644 > --- a/drivers/clocksource/timer-imx-sysctr.c > +++ b/drivers/clocksource/timer-imx-sysctr.c > @@ -8,9 +8,12 @@ > #include "timer-of.h" > > #define CMP_OFFSET 0x10000 > +#define RD_OFFSET 0x20000 > > #define CNTCV_LO 0x8 > #define CNTCV_HI 0xc > +#define CNTCV_LO_IMX95 (RD_OFFSET + 0x8) > +#define CNTCV_HI_IMX95 (RD_OFFSET + 0xc) > #define CMPCV_LO (CMP_OFFSET + 0x20) > #define CMPCV_HI (CMP_OFFSET + 0x24) > #define CMPCR (CMP_OFFSET + 0x2c) > @@ -22,6 +25,8 @@ > > static void __iomem *sys_ctr_base __ro_after_init; > static u32 cmpcr __ro_after_init; > +static u32 cntcv_hi = CNTCV_HI; > +static u32 cntcv_lo = CNTCV_LO; > > static void sysctr_timer_enable(bool enable) > { > @@ -43,9 +48,9 @@ static inline u64 sysctr_read_counter(void) > u32 cnt_hi, tmp_hi, cnt_lo; > > do { > - cnt_hi = readl_relaxed(sys_ctr_base + CNTCV_HI); > - cnt_lo = readl_relaxed(sys_ctr_base + CNTCV_LO); > - tmp_hi = readl_relaxed(sys_ctr_base + CNTCV_HI); > + cnt_hi = readl_relaxed(sys_ctr_base + cntcv_hi); > + cnt_lo = readl_relaxed(sys_ctr_base + cntcv_lo); > + tmp_hi = readl_relaxed(sys_ctr_base + cntcv_hi); > } while (tmp_hi != cnt_hi); > > return ((u64) cnt_hi << 32) | cnt_lo; > @@ -139,6 +144,11 @@ static int __init sysctr_timer_init(struct device_node *np) > to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV; > } > > + if (of_device_is_compatible(np, "nxp,imx95-sysctr-timer")) { > + cntcv_hi = CNTCV_HI_IMX95; > + cntcv_lo = CNTCV_LO_IMX95; > + } I'm not a fan of this, since TIMER_OF_DECLARE() can do the compat check. So instead of using fallback bindings just use the correct binding within the dts file. Also I'm not a fan of this clobal variable setting albeit there is just one instance _yet_ we really should instead rework this driver a bit and instead provide a i.MX95 specific sysctr_read_counter() function. This is clearly a bit more work but IMO a cleaner approach. Also afterwards once you add i.MX9x which is again a bit different would gain from this work. Regards, Marco > + > sys_ctr_base = timer_of_base(&to_sysctr); > cmpcr = readl(sys_ctr_base + CMPCR); > cmpcr &= ~SYS_CTR_EN; > -- > 2.37.1 > > >