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Message-ID: <effe9e2c56baca76cbef09b0262c246478670bc2.camel@ew.tq-group.com>
Subject: Re: [PATCH] powerpc/6xx: set High BAT Enable flag on G2 cores
From: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
To: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Nicholas Piggin <npiggin@gmail.com>, "Aneesh Kumar K.V"
 <aneesh.kumar@kernel.org>, "Naveen N. Rao" <naveen.n.rao@linux.ibm.com>, 
 "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
 "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
 "linux@ew.tq-group.com" <linux@ew.tq-group.com>,  Michael Ellerman
 <mpe@ellerman.id.au>
Date: Tue, 23 Jan 2024 13:05:30 +0100
In-Reply-To: <f8c2f1c8-0b43-47c6-9359-9aeeb14863eb@csgroup.eu>
References: <20231221124538.159706-1-matthias.schiffer@ew.tq-group.com>
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On Fri, 2024-01-19 at 13:53 +0000, Christophe Leroy wrote:
>=20
> Le 19/01/2024 =C3=A0 14:41, Matthias Schiffer a =C3=A9crit=C2=A0:
> > >=20
> > > Thinking about it once more, can we do even more simple ?
> > >=20
> > > Why do we need that __setup_cpu_g2() at all ?
> > >=20
> > > You could just add the following into __set_cpu_603()
> > >=20
> > > diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S
> > > b/arch/powerpc/kernel/cpu_setup_6xx.S
> > > index c67d32e04df9..7b41e3884866 100644
> > > --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> > > +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> > > @@ -21,6 +21,11 @@ BEGIN_MMU_FTR_SECTION
> > >        li      r10,0
> > >        mtspr   SPRN_SPRG_603_LRU,r10           /* init SW LRU trackin=
g */
> > >    END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
> > > +BEGIN_MMU_FTR_SECTION
> > > +     mfspr   r11,SPRN_HID2_G2
> > > +     oris    r11,r11,HID2_HBE_G2@h
> > > +     mtspr   SPRN_HID2_G2,r11
> > > +END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
> > >=20
> > >    BEGIN_FTR_SECTION
> > >        bl      __init_fpu_registers
> > > ---
> > >=20
> > > By the way, as your register is named SPRN_HID2_G2, the bit would bet=
ter
> > > be named HID2_G2_HBE instead of HID2_HBE_G2 I think.
> >=20
> > My intention was to keep this consistent with the SPRN_HID2_GEKKO defin=
e.
>=20
> I don't understand what you mean. I can't see any bits defined for=20
> HID2_GEKKO.
>=20
> What I see which is simitar is the definition of TSC register for CELL CP=
U.
>=20
> #define SPRN_TSC_CELL	0x399	/* Thread switch control on Cell */
> #define   TSC_CELL_DEC_ENABLE_0	0x400000 /* Decrementer Interrupt */
> #define   TSC_CELL_DEC_ENABLE_1	0x200000 /* Decrementer Interrupt */
> #define   TSC_CELL_EE_ENABLE	0x100000 /* External Interrupt */
> #define   TSC_CELL_EE_BOOST	0x080000 /* External Interrupt Boost */
>=20
>=20
> They don't call it TSC_EE_BOOST_CELL or TSC_EE_ENABLE_CELL

Ah sorry, I got things mixed up. Will change the define to HID2_G2_HBE (or =
maybe HID_G2_LE_HBE?)
in v2.

Regards,
Matthias


>=20
>=20
> Christophe
>=20
> >=20
> > Regards,
> > Matthias
> >=20
> >=20
> >=20
> >=20
> > >=20
> > > Christophe
> > >=20
> > > >=20
> > > > >=20
> > > > > > +
> > > > > > +BEGIN_FTR_SECTION
> > > > > > +       bl      __init_fpu_registers
> > > > > > +END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
> > > > > > +       bl      setup_common_caches
> > > > > > +       bl      setup_g2_hid2
> > > > > > +       mtlr    r5
> > > > > > +       blr
> > > > > >=20
> > > > > >     /* Enable caches for 603's, 604, 750 & 7400 */
> > > > > >     SYM_FUNC_START_LOCAL(setup_common_caches)
> > > > > > @@ -115,6 +129,16 @@ SYM_FUNC_START_LOCAL(setup_604_hid0)
> > > > > >            blr
> > > > > >     SYM_FUNC_END(setup_604_hid0)
> > > > > >=20
> > > > > > +/* Enable high BATs for G2 (G2_LE, e300cX) */
> > > > > > +SYM_FUNC_START_LOCAL(setup_g2_hid2)
> > > > > > +       mfspr   r11,SPRN_HID2_G2
> > > > > > +       oris    r11,r11,HID2_HBE_G2@h
> > > > > > +       mtspr   SPRN_HID2_G2,r11
> > > > > > +       sync
> > > > > > +       isync
> > > > > > +       blr
> > > > > > +SYM_FUNC_END(setup_g2_hid2)
> > > > > > +
> > > > > >     /* 7400 <=3D rev 2.7 and 7410 rev =3D 1.0 suffer from some
> > > > > >      * erratas we work around here.
> > > > > >      * Moto MPC710CE.pdf describes them, those are errata
> > > > > > @@ -495,4 +519,3 @@ _GLOBAL(__restore_cpu_setup)
> > > > > >            mtcr    r7
> > > > > >            blr
> > > > > >     _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup)
> > > > > > -
> > > > > > diff --git a/arch/powerpc/kernel/cpu_specs_book3s_32.h b/arch/p=
owerpc/kernel/cpu_specs_book3s_32.h
> > > > > > index 3714634d194a1..83f054fcf837c 100644
> > > > > > --- a/arch/powerpc/kernel/cpu_specs_book3s_32.h
> > > > > > +++ b/arch/powerpc/kernel/cpu_specs_book3s_32.h
> > > > > > @@ -69,7 +69,7 @@ static struct cpu_spec cpu_specs[] __initdata=
 =3D {
> > > > > >                    .mmu_features           =3D MMU_FTR_USE_HIGH=
_BATS,
> > > > > >                    .icache_bsize           =3D 32,
> > > > > >                    .dcache_bsize           =3D 32,
> > > > > > -               .cpu_setup              =3D __setup_cpu_603,
> > > > > > +               .cpu_setup              =3D __setup_cpu_g2,
> > > > > >                    .machine_check          =3D machine_check_ge=
neric,
> > > > > >                    .platform               =3D "ppc603",
> > > > > >            },
> > > > > > @@ -83,7 +83,7 @@ static struct cpu_spec cpu_specs[] __initdata=
 =3D {
> > > > > >                    .mmu_features           =3D MMU_FTR_USE_HIGH=
_BATS,
> > > > > >                    .icache_bsize           =3D 32,
> > > > > >                    .dcache_bsize           =3D 32,
> > > > > > -               .cpu_setup              =3D __setup_cpu_603,
> > > > > > +               .cpu_setup              =3D __setup_cpu_g2,
> > > > > >                    .machine_check          =3D machine_check_83=
xx,
> > > > > >                    .platform               =3D "ppc603",
> > > > > >            },
> > > > > > @@ -96,7 +96,7 @@ static struct cpu_spec cpu_specs[] __initdata=
 =3D {
> > > > > >                    .mmu_features           =3D MMU_FTR_USE_HIGH=
_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > >                    .icache_bsize           =3D 32,
> > > > > >                    .dcache_bsize           =3D 32,
> > > > > > -               .cpu_setup              =3D __setup_cpu_603,
> > > > > > +               .cpu_setup              =3D __setup_cpu_g2,
> > > > > >                    .machine_check          =3D machine_check_83=
xx,
> > > > > >                    .platform               =3D "ppc603",
> > > > > >            },
> > > > > > @@ -109,7 +109,7 @@ static struct cpu_spec cpu_specs[] __initda=
ta =3D {
> > > > > >                    .mmu_features           =3D MMU_FTR_USE_HIGH=
_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > >                    .icache_bsize           =3D 32,
> > > > > >                    .dcache_bsize           =3D 32,
> > > > > > -               .cpu_setup              =3D __setup_cpu_603,
> > > > > > +               .cpu_setup              =3D __setup_cpu_g2,
> > > > > >                    .machine_check          =3D machine_check_83=
xx,
> > > > > >                    .num_pmcs               =3D 4,
> > > > > >                    .platform               =3D "ppc603",
> > > > > > @@ -123,7 +123,7 @@ static struct cpu_spec cpu_specs[] __initda=
ta =3D {
> > > > > >                    .mmu_features           =3D MMU_FTR_USE_HIGH=
_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > >                    .icache_bsize           =3D 32,
> > > > > >                    .dcache_bsize           =3D 32,
> > > > > > -               .cpu_setup              =3D __setup_cpu_603,
> > > > > > +               .cpu_setup              =3D __setup_cpu_g2,
> > > > > >                    .machine_check          =3D machine_check_83=
xx,
> > > > > >                    .num_pmcs               =3D 4,
> > > > > >                    .platform               =3D "ppc603",
> > > > > > --
> > > > > > TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 S=
eefeld, Germany
> > > > > > Amtsgericht M=C3=BCnchen, HRB 105018
> > > > > > Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl=
, Stefan Schneider
> > > > > > https://www.tq-group.com/
> > > >=20
> > > > --
> > > > TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefe=
ld, Germany
> > > > Amtsgericht M=C3=BCnchen, HRB 105018
> > > > Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, St=
efan Schneider
> > > > https://www.tq-group.com/
> >=20
> > --
> > TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, =
Germany
> > Amtsgericht M=C3=BCnchen, HRB 105018
> > Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan=
 Schneider
> > https://www.tq-group.com/
>=20

--=20
TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ=
any
Amtsgericht M=C3=BCnchen, HRB 105018
Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch=
neider
https://www.tq-group.com/